Accesses to the PTP_RTC_SUB_NANOSEC register are done through a
hardcoded address which doesn't match with the KSZ8463's register
layout.
Add a new entry for the PTP_RTC_SUB_NANOSEC register in the regs[]
tables.
Use the regs[] table to retrieve the PTP_RTC_SUB_NANOSEC register
address when accessing it.
Remove the macro defining the address to prevent further use.
Signed-off-by: Bastien Curutchet (Schneider Electric) <bastien.curutchet@bootlin.com>
Link: https://patch.msgid.link/20260105-ksz-rework-v1-6-a68df7f57375@bootlin.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
[PTP_CLK_CTRL] = 0x0600,
[PTP_RTC_NANOSEC] = 0x0604,
[PTP_RTC_SEC] = 0x0608,
+ [PTP_RTC_SUB_NANOSEC] = 0x060C,
};
static const u32 ksz8463_masks[] = {
[REG_PORT_PME_STATUS] = 0x0013,
[REG_PORT_PME_CTRL] = 0x0017,
[PTP_CLK_CTRL] = 0x0500,
+ [PTP_RTC_SUB_NANOSEC] = 0x0502,
[PTP_RTC_NANOSEC] = 0x0504,
[PTP_RTC_SEC] = 0x0508,
};
PTP_CLK_CTRL,
PTP_RTC_NANOSEC,
PTP_RTC_SEC,
+ PTP_RTC_SUB_NANOSEC,
};
enum ksz_masks {
if (ret)
return ret;
- ret = ksz_read8(dev, REG_PTP_RTC_SUB_NANOSEC__2, &phase);
+ ret = ksz_read8(dev, regs[PTP_RTC_SUB_NANOSEC], &phase);
if (ret)
return ret;
mutex_lock(&ptp_data->lock);
/* Write to shadow registers and Load PTP clock */
- ret = ksz_write16(dev, REG_PTP_RTC_SUB_NANOSEC__2, PTP_RTC_0NS);
+ ret = ksz_write16(dev, regs[PTP_RTC_SUB_NANOSEC], PTP_RTC_0NS);
if (ret)
goto unlock;
#define PTP_CLK_ENABLE BIT(1)
#define PTP_CLK_RESET BIT(0)
-#define REG_PTP_RTC_SUB_NANOSEC__2 0x0502
-
+/* REG_PTP_RTC_SUB_NANOSEC */
#define PTP_RTC_SUB_NANOSEC_M 0x0007
#define PTP_RTC_0NS 0x00