]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
net: dsa: microchip: Use regs[] to access REG_PTP_RTC_SUB_NANOSEC
authorBastien Curutchet (Schneider Electric) <bastien.curutchet@bootlin.com>
Mon, 5 Jan 2026 13:08:05 +0000 (14:08 +0100)
committerPaolo Abeni <pabeni@redhat.com>
Thu, 8 Jan 2026 12:01:16 +0000 (13:01 +0100)
Accesses to the PTP_RTC_SUB_NANOSEC register are done through a
hardcoded address which doesn't match with the KSZ8463's register
layout.

Add a new entry for the PTP_RTC_SUB_NANOSEC register in the regs[]
tables.
Use the regs[] table to retrieve the PTP_RTC_SUB_NANOSEC register
address when accessing it.
Remove the macro defining the address to prevent further use.

Signed-off-by: Bastien Curutchet (Schneider Electric) <bastien.curutchet@bootlin.com>
Link: https://patch.msgid.link/20260105-ksz-rework-v1-6-a68df7f57375@bootlin.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
drivers/net/dsa/microchip/ksz_common.c
drivers/net/dsa/microchip/ksz_common.h
drivers/net/dsa/microchip/ksz_ptp.c
drivers/net/dsa/microchip/ksz_ptp_reg.h

index 595438031d316eda96ee7fa781aebdb65575b336..7af008cafccf716c2114f486938cdc25b7daae73 100644 (file)
@@ -572,6 +572,7 @@ static const u16 ksz8463_regs[] = {
        [PTP_CLK_CTRL]                  = 0x0600,
        [PTP_RTC_NANOSEC]               = 0x0604,
        [PTP_RTC_SEC]                   = 0x0608,
+       [PTP_RTC_SUB_NANOSEC]           = 0x060C,
 };
 
 static const u32 ksz8463_masks[] = {
@@ -807,6 +808,7 @@ static const u16 ksz9477_regs[] = {
        [REG_PORT_PME_STATUS]           = 0x0013,
        [REG_PORT_PME_CTRL]             = 0x0017,
        [PTP_CLK_CTRL]                  = 0x0500,
+       [PTP_RTC_SUB_NANOSEC]           = 0x0502,
        [PTP_RTC_NANOSEC]               = 0x0504,
        [PTP_RTC_SEC]                   = 0x0508,
 };
index b4305bd47fbebfd917fca978a6f916d13b6115ea..d1baa3ce09b5fee8e0984791a730b70b704fcfdd 100644 (file)
@@ -274,6 +274,7 @@ enum ksz_regs {
        PTP_CLK_CTRL,
        PTP_RTC_NANOSEC,
        PTP_RTC_SEC,
+       PTP_RTC_SUB_NANOSEC,
 };
 
 enum ksz_masks {
index 5a94beb410df38f5d0465e1cd896039292f9a5ec..3766d8bde478e6c2cf0ec19e7ac27570c2bb7676 100644 (file)
@@ -596,7 +596,7 @@ static int _ksz_ptp_gettime(struct ksz_device *dev, struct timespec64 *ts)
        if (ret)
                return ret;
 
-       ret = ksz_read8(dev, REG_PTP_RTC_SUB_NANOSEC__2, &phase);
+       ret = ksz_read8(dev, regs[PTP_RTC_SUB_NANOSEC], &phase);
        if (ret)
                return ret;
 
@@ -683,7 +683,7 @@ static int ksz_ptp_settime(struct ptp_clock_info *ptp,
        mutex_lock(&ptp_data->lock);
 
        /* Write to shadow registers and Load PTP clock */
-       ret = ksz_write16(dev, REG_PTP_RTC_SUB_NANOSEC__2, PTP_RTC_0NS);
+       ret = ksz_write16(dev, regs[PTP_RTC_SUB_NANOSEC], PTP_RTC_0NS);
        if (ret)
                goto unlock;
 
index d1d31514488609df9f5eee4b12bff074965b1c6e..41891ddadaa30ce2cf3ac41273fd335987258230 100644 (file)
@@ -24,8 +24,7 @@
 #define PTP_CLK_ENABLE                 BIT(1)
 #define PTP_CLK_RESET                  BIT(0)
 
-#define REG_PTP_RTC_SUB_NANOSEC__2     0x0502
-
+/* REG_PTP_RTC_SUB_NANOSEC */
 #define PTP_RTC_SUB_NANOSEC_M          0x0007
 #define PTP_RTC_0NS                    0x00