drm/amd/display: Check null pointers before used

[ Upstream commit be1fb44389ca3038ad2430dac4234669bc177ee3 ]

[WHAT & HOW]
Poniters, such as dc->clk_mgr, are null checked previously in the same
function, so Coverity warns "implies that "dc->clk_mgr" might be null".
As a result, these pointers need to be checked when used again.

This fixes 10 FORWARD_NULL issues reported by Coverity.

Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
index 78df96882d6ec5c8540e31a819dd7fbfd46b5e4f..f8409453434c1cfacfd8b3cfda078f67727c0281 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
@@ -195,7 +195,7 @@ void dce11_pplib_apply_display_requirements(
         * , then change minimum memory clock based on real-time bandwidth
         * limitation.
         */
-       if ((dc->ctx->asic_id.chip_family == FAMILY_AI) &&
+       if (dc->bw_vbios && (dc->ctx->asic_id.chip_family == FAMILY_AI) &&
             ASICREV_IS_VEGA20_P(dc->ctx->asic_id.hw_internal_rev) && (context->stream_count >= 2)) {
                pp_display_cfg->min_memory_clock_khz = max(pp_display_cfg->min_memory_clock_khz,
                                                           (uint32_t) div64_s64(

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
index bf399819ca800e08806ad0e38fc87e923bdbaee7..22ac2b7e49aeae66e6ce182f77be943df14151f4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c
@@ -749,7 +749,8 @@ bool hubp1_is_flip_pending(struct hubp *hubp)
        if (flip_pending)
                return true;
 
-       if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)
+       if (hubp &&
+           earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)
                return true;
 
        return false;

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
index 6bba020ad6fbfe7d8a453214a5a38ef3c449ab40..0637e4c552d8a29cda4bb087b391b2d6d7305805 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
@@ -927,7 +927,8 @@ bool hubp2_is_flip_pending(struct hubp *hubp)
        if (flip_pending)
                return true;
 
-       if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)
+       if (hubp &&
+           earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)
                return true;
 
        return false;

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index fc0d2077aaec4708792aff837e807cf7dff8ac13..96371dac72fc108a9dc074a9abf12d7acc59a5cf 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -950,7 +950,7 @@ void dce110_edp_backlight_control(
 {
        struct dc_context *ctx = link->ctx;
        struct bp_transmitter_control cntl = { 0 };
-       uint8_t pwrseq_instance;
+       uint8_t pwrseq_instance = 0;
        unsigned int pre_T11_delay = OLED_PRE_T11_DELAY;
        unsigned int post_T7_delay = OLED_POST_T7_DELAY;
 
@@ -1003,7 +1003,8 @@ void dce110_edp_backlight_control(
         */
        /* dc_service_sleep_in_milliseconds(50); */
                /*edp 1.2*/
-       pwrseq_instance = link->panel_cntl->pwrseq_inst;
+       if (link->panel_cntl)
+               pwrseq_instance = link->panel_cntl->pwrseq_inst;
 
        if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) {
                if (!link->dc->config.edp_no_power_sequencing)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index 1d2be574f6680963a6aee6618f2d15125d11497a..83942abd08e84807e4c6f7ac1bc3515cff58bf10 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -1554,7 +1554,7 @@ void dcn10_init_hw(struct dc *dc)
                dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
 
        /* Align bw context with hw config when system resume. */
-       if (dc->clk_mgr->clks.dispclk_khz != 0 && dc->clk_mgr->clks.dppclk_khz != 0) {
+       if (dc->clk_mgr && dc->clk_mgr->clks.dispclk_khz != 0 && dc->clk_mgr->clks.dppclk_khz != 0) {
                dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz = dc->clk_mgr->clks.dispclk_khz;
                dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz = dc->clk_mgr->clks.dppclk_khz;
        }
@@ -1674,7 +1674,7 @@ void dcn10_init_hw(struct dc *dc)
                REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
        }
 
-       if (dc->clk_mgr->funcs->notify_wm_ranges)
+       if (dc->clk_mgr && dc->clk_mgr->funcs->notify_wm_ranges)
                dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
index 746c522adf84cad68dcf63cf29df9b8c042499d0..3d4b31bd994691fc5d7f0823639fed628c8ed2d6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
@@ -256,10 +256,10 @@ void dcn31_init_hw(struct dc *dc)
        if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
                dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
 
-       if (dc->clk_mgr->funcs->notify_wm_ranges)
+       if (dc->clk_mgr && dc->clk_mgr->funcs->notify_wm_ranges)
                dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
 
-       if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)
+       if (dc->clk_mgr && dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)
                dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
 
        if (dc->res_pool->hubbub->funcs->force_pstate_change_control)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index 80db40787e019768e7ce672f7989644dd03cfc8b..12a39dbc35419eb7044c212256017aea9c542cfc 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -235,7 +235,7 @@ void dcn35_init_hw(struct dc *dc)
        if (hws->funcs.enable_power_gating_plane)
                hws->funcs.enable_power_gating_plane(dc->hwseq, true);
 */
-       if (res_pool->hubbub->funcs->dchubbub_init)
+       if (res_pool->hubbub && res_pool->hubbub->funcs->dchubbub_init)
                res_pool->hubbub->funcs->dchubbub_init(dc->res_pool->hubbub);
        /* If taking control over from VBIOS, we may want to optimize our first
         * mode set, so we need to skip powering down pipes until we know which
@@ -328,10 +328,10 @@ void dcn35_init_hw(struct dc *dc)
        if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
                dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
 
-       if (dc->clk_mgr->funcs->notify_wm_ranges)
+       if (dc->clk_mgr && dc->clk_mgr->funcs->notify_wm_ranges)
                dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);
 
-       if (dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)
+       if (dc->clk_mgr && dc->clk_mgr->funcs->set_hard_max_memclk && !dc->clk_mgr->dc_mode_softmax_enabled)
                dc->clk_mgr->funcs->set_hard_max_memclk(dc->clk_mgr);
 
 
@@ -1054,7 +1054,7 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,
                if (pipe_ctx->plane_res.hubp)
                        update_state->pg_pipe_res_update[PG_HUBP][pipe_ctx->plane_res.hubp->inst] = false;
 
-               if (pipe_ctx->plane_res.dpp)
+               if (pipe_ctx->plane_res.dpp && pipe_ctx->plane_res.hubp)
                        update_state->pg_pipe_res_update[PG_DPP][pipe_ctx->plane_res.hubp->inst] = false;
 
                if (pipe_ctx->plane_res.dpp || pipe_ctx->stream_res.opp)

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
index 46bb7a855bc218bf0f44cb1bf0d7ac38a9e3d9cb..60015e94c4aa8c927e150061ce14af46db5182e9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
@@ -2254,7 +2254,7 @@ bool dp_verify_link_cap_with_retries(
 
                memset(&link->verified_link_cap, 0,
                                sizeof(struct dc_link_settings));
-               if (!link_detect_connection_type(link, &type) || type == dc_connection_none) {
+               if (link->link_enc && (!link_detect_connection_type(link, &type) || type == dc_connection_none)) {
                        link->verified_link_cap = fail_safe_link_settings;
                        break;
                } else if (dp_verify_link_cap(link, known_limit_link_setting, &fail_count)) {