amdgcn: Mark s_mulk_i32 as clobbering SCC

The s_mulk_i32 instruction sets the SCC status register according to
whether the multiplication overflows, but that is not currently modelled
in the GCN backend.  AFAIK this is a latent bug and hasn't been noticed
"in the wild", but it should be fixed.

2021-06-29  Julian Brown  <julian@codesourcery.com>

gcc/
	* config/gcn/gcn.md (mulsi3): Make s_mulk_i32 variant clobber SCC.

(cherry picked from commit 5c127c4cac308429cba483a2ac4e175c2ab26165)

diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md
index 57a3a58c7d635eeab88a7c1407adc099fb5dbf63..d41ce6c80a2753a2c920ad11d41325d95a9b2159 100644 (file)
--- a/gcc/config/gcn/gcn.md
+++ b/gcc/config/gcn/gcn.md
@@ -1372,10 +1372,13 @@
 
 ; Vector multiply has vop3a encoding, but no corresponding vop2a, so no long
 ; immediate.
+; The "s_mulk_i32" variant sets SCC to indicate overflow (which we don't care
+; about here, but we need to indicate the clobbering).
 (define_insn "mulsi3"
   [(set (match_operand:SI 0 "register_operand"        "= Sg,Sg, Sg,   v")
         (mult:SI (match_operand:SI 1 "gcn_alu_operand" "%SgA, 0,SgA,   v")
-                (match_operand:SI 2 "gcn_alu_operand" " SgA, J,  B,vASv")))]
+                (match_operand:SI 2 "gcn_alu_operand" " SgA, J,  B,vASv")))
+   (clobber (match_scratch:BI 3                                 "=X,cs,  X,   X"))]
   ""
   "@
    s_mul_i32\t%0, %1, %2