docs/system/arm/xlnx-zynq.rst: Improve docs rendering

Make some minor improvements to the rendering of the docs for
the xlnx-zynq-a9 board:

 * use a proper hyperlink rather than a bare URL for the
   link to the reference manual
 * drop the hex address of the SMC SRAM: the bare '@' is
   rendered as bogus mailto: hyperlink, and the information
   is not very interesting to the user anyway
 * expand out the abbreviations in the list of Cortex-A9
   per-CPU devices
 * correct the bullet-point list markup so it doesn't render
   with odd highlighted lines
 * capitalize 'Arm' correctly

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Zhang Chen <zhangckid@gmail.com>
Message-id: 20260115142629.665319-2-peter.maydell@linaro.org

diff --git a/docs/system/arm/xlnx-zynq.rst b/docs/system/arm/xlnx-zynq.rst
index ade18a3fe1306fe6b7ca48ee5d5f9f574a24e97e..aa37df2926664c45584457d02cb1071d25994727 100644 (file)
--- a/docs/system/arm/xlnx-zynq.rst
+++ b/docs/system/arm/xlnx-zynq.rst
@@ -4,32 +4,35 @@ The Zynq 7000 family is based on the AMD SoC architecture. These products
 integrate a feature-rich dual or single-core Arm Cortex-A9 MPCore based
 processing system (PS) and AMD programmable logic (PL) in a single device.
 
-More details here:
-https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Zynq-7000-SoC-Technical-Reference-Manual
-
-QEMU xilinx-zynq-a9 board supports following devices:
-    - A9 MPCORE
-        - cortex-a9
-        - GIC v1
-        - Generic timer
-        - wdt
-    - OCM 256KB
-    - SMC SRAM@0xe2000000 64MB
-    - Zynq SLCR
-    - SPI x2
-    - QSPI
-    - UART
-    - TTC x2
-    - Gigabit Ethernet Controller x2
-    - SD Controller x2
-    - XADC
-    - Arm PrimeCell DMA Controller
-    - DDR Memory
-    - USB 2.0 x2
+The SoC is documented in the
+`Zynq 7000 Technical Reference manual <https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Zynq-7000-SoC-Technical-Reference-Manual>`__.
+
+The QEMU xilinx-zynq-a9 board supports the following devices:
+
+- Arm Cortex-A9 MPCore CPU
+
+  - Cortex-A9 CPUs
+  - GIC v1 interrupt controller
+  - Generic timer
+  - Watchdog timer
+
+- OCM 256KB
+- SMC SRAM 64MB
+- Zynq SLCR
+- SPI x2
+- QSPI
+- UART
+- TTC x2
+- Gigabit Ethernet Controller x2
+- SD Controller x2
+- XADC
+- Arm PrimeCell DMA Controller
+- DDR Memory
+- USB 2.0 x2
 
 Running
 """""""
-Direct Linux boot of a generic ARM upstream Linux kernel:
+Direct Linux boot of a generic Arm upstream Linux kernel:
 
 .. code-block:: bash
 
@@ -44,4 +47,4 @@ For configuring the boot-mode provide the following on the command line:
 
    -machine boot-mode=qspi
 
-Supported values are jtag, sd, qspi, nor.
+Supported values are ``jtag``, ``sd``, ``qspi`` and ``nor``.