RISC-V: Fix zero-scratch-regs-3.c fail

gcc/ChangeLog:

	* config/riscv/riscv.cc (vector_zero_call_used_regs): Add
	explict VL and drop VL in ops.

Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 09fc9e5d95e611f94bc05b4851fef6f50a651c28..b16c60df6a7565828b7fc6ef10b122bfccccc5d3 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7396,9 +7396,9 @@ vector_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)
              emitted_vlmax_vsetvl = true;
            }
 
-         rtx ops[] = {target, CONST0_RTX (mode), vl};
+         rtx ops[] = {target, CONST0_RTX (mode)};
          riscv_vector::emit_vlmax_insn (code_for_pred_mov (mode),
-                                        riscv_vector::RVV_UNOP, ops);
+                                        riscv_vector::RVV_UNOP, ops, vl);
 
          SET_HARD_REG_BIT (zeroed_hardregs, regno);
        }