sse.md (sse3_mwait): Swap the operand constriants.

2015-06-08  Venkataramanan Kumar  <venkataramanan.kumar@amd.com>

        * config/i386/sse.md (sse3_mwait): Swap the operand constriants.

From-SVN: r224214

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 512d82789ee7184438bca99f8eb720314599fa4f..09dbbcb4582508f34205c94cf948ecd4344e4775 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2015-06-08  Venkataramanan Kumar  <venkataramanan.kumar@amd.com>
+
+       * config/i386/sse.md (sse3_mwait): Swap the operand constriants.
+
 2015-06-03  Jakub Jelinek  <jakub@redhat.com>
 
        Backported from mainline

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 5973b3423b056f8ef4c3b1e42b93eb3eb2c3044a..8f5120f2ef7340542263f1ba8b157d2fe2e6e2e6 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -10837,10 +10837,12 @@
    (set_attr "atom_sse_attr" "fence")
    (set_attr "memory" "unknown")])
 
-
+;; As per AMD and Intel ISA manuals, the first operand is extensions
+;; and it goes to %ecx. The second operand received is hints and it goes
+;; to %eax.
 (define_insn "sse3_mwait"
-  [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
-                    (match_operand:SI 1 "register_operand" "c")]
+  [(unspec_volatile [(match_operand:SI 0 "register_operand" "c")
+                    (match_operand:SI 1 "register_operand" "a")]
                    UNSPECV_MWAIT)]
   "TARGET_SSE3"
 ;; 64bit version is "mwait %rax,%rcx". But only lower 32bits are used.