perf/x86/intel: Consolidate MSR_IA32_PERF_CFG_C tracking

Both Auto Counter Reload (ACR) and Architectural PEBS use the PERF_CFG_C
MSRs to configure event behavior. Currently, the driver maintains two
independent variables acr_cfg_c and cfg_c_val to cache the values intended
for these MSRs.

Using separate variables to track a single hardware register state is
error-prone and can lead to configuration conflicts. Consolidate the
tracking into a single cfg_c_val variable to ensure a unified and
consistent view of the PERF_CFG_C MSR state.

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260430002558.712334-6-dapeng1.mi@linux.intel.com

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index dd1e3aa75ee9b739fe2b61a24134c2ed35e65440..2b05587c84f74918b575502384447afbb0aeb410 100644 (file)
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3169,10 +3169,10 @@ static void intel_pmu_config_acr(int idx, u64 mask, u32 reload)
                wrmsrl(msr_b + msr_offset, mask);
                cpuc->acr_cfg_b[idx] = mask;
        }
-       /* Only need to update the reload value when there is a valid config value. */
-       if (mask && cpuc->acr_cfg_c[idx] != reload) {
+       /* Only update CFG_C reload when ACR is actively enabled (mask != 0) */
+       if (mask && ((cpuc->cfg_c_val[idx] & ARCH_PEBS_RELOAD) != reload)) {
                wrmsrl(msr_c + msr_offset, reload);
-               cpuc->acr_cfg_c[idx] = reload;
+               cpuc->cfg_c_val[idx] = reload;
        }
 }
 
@@ -3198,14 +3198,15 @@ static void intel_pmu_enable_event_ext(struct perf_event *event)
 {
        struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
        struct hw_perf_event *hwc = &event->hw;
-       union arch_pebs_index old, new;
-       struct arch_pebs_cap cap;
        u64 ext = 0;
 
-       cap = hybrid(cpuc->pmu, arch_pebs_cap);
+       if (is_acr_event_group(event))
+               ext |= (-hwc->sample_period) & ARCH_PEBS_RELOAD;
 
        if (event->attr.precise_ip) {
                u64 pebs_data_cfg = intel_get_arch_pebs_data_config(event);
+               struct arch_pebs_cap cap = hybrid(cpuc->pmu, arch_pebs_cap);
+               union arch_pebs_index old, new;
 
                ext |= ARCH_PEBS_EN;
                if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD)

diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 524668dcf4cc10bb2efd61249b8d137e8dd37104..40d6fe0afc4ab6d041baaba606abd2e7fd4d271b 100644 (file)
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -322,10 +322,8 @@ struct cpu_hw_events {
        u64                     fixed_ctrl_val;
        u64                     active_fixed_ctrl_val;
 
-       /* Intel ACR configuration */
+       /* Intel ACR/arch-PEBS configuration */
        u64                     acr_cfg_b[X86_PMC_IDX_MAX];
-       u64                     acr_cfg_c[X86_PMC_IDX_MAX];
-       /* Cached CFG_C values */
        u64                     cfg_c_val[X86_PMC_IDX_MAX];
 
        /*