aarch64: Relax FP/vector register matches

There were many tests that used [0-9] to match an FP or vector register,
but that should allow any of 0-31 instead.

asm-x-constraint-1.c required s0-s7, but that's the range for "y"
rather than "x".  "x" allows s0-s15.

sve/pcs/return_9.c required z2-z7 (the initial set of available
call-clobbered registers), but z24-z31 are OK too.

gcc/testsuite/
	* gcc.target/aarch64/advsimd-intrinsics/vshl-opt-6.c: Allow any
	FP/vector register, not just register 0-9.
	* gcc.target/aarch64/fmul_fcvt_2.c: Likewise.
	* gcc.target/aarch64/ldp_stp_8.c: Likewise.
	* gcc.target/aarch64/ldp_stp_17.c: Likewise.
	* gcc.target/aarch64/ldp_stp_21.c: Likewise.
	* gcc.target/aarch64/simd/vpaddd_f64.c: Likewise.
	* gcc.target/aarch64/simd/vpaddd_s64.c: Likewise.
	* gcc.target/aarch64/simd/vpaddd_u64.c: Likewise.
	* gcc.target/aarch64/sve/adr_1.c: Likewise.
	* gcc.target/aarch64/sve/adr_2.c: Likewise.
	* gcc.target/aarch64/sve/adr_3.c: Likewise.
	* gcc.target/aarch64/sve/adr_4.c: Likewise.
	* gcc.target/aarch64/sve/adr_5.c: Likewise.
	* gcc.target/aarch64/sve/extract_1.c: Likewise.
	* gcc.target/aarch64/sve/extract_2.c: Likewise.
	* gcc.target/aarch64/sve/extract_3.c: Likewise.
	* gcc.target/aarch64/sve/extract_4.c: Likewise.
	* gcc.target/aarch64/sve/slp_4.c: Likewise.
	* gcc.target/aarch64/sve/spill_3.c: Likewise.
	* gcc.target/aarch64/vfp-1.c: Likewise.
	* gcc.target/aarch64/asm-x-constraint-1.c: Allow s0-s15, not just
	s0-s7.
	* gcc.target/aarch64/sve/pcs/return_9.c: Allow z24-z31 as well as
	z2-z7.

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl-opt-6.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl-opt-6.c
index 442e3163237e55978487f7fde798c98d3ffdd633..3eff71b53fa5ac28abead4e9f68e86f37d0c213e 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl-opt-6.c
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshl-opt-6.c
@@ -7,4 +7,4 @@ int32x4_t foo (int32x4_t x) {
   return vshlq_s32(x, vdupq_n_s32(256));
 }
 
-/* { dg-final { scan-assembler-times {\tsshl\t.+, v[0-9].4s} 1 } } */
+/* { dg-final { scan-assembler-times {\tsshl\t.+, v[0-9]+.4s} 1 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/asm-x-constraint-1.c b/gcc/testsuite/gcc.target/aarch64/asm-x-constraint-1.c
index a71043be504eb203d62580de1ac05359160d63ac..ecfb01d247e740d32f969bb38284640987a1e884 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/asm-x-constraint-1.c
+++ b/gcc/testsuite/gcc.target/aarch64/asm-x-constraint-1.c
@@ -28,7 +28,7 @@ f (void)
 /* { dg-final { scan-assembler {\t// s7 out: s7\n.*[/]/ s7 in: s7\n} } } */
 /* { dg-final { scan-assembler {\t// s8 out: s8\n.*[/]/ s8 in: s8\n} } } */
 /* { dg-final { scan-assembler {\t// s15 out: s15\n.*[/]/ s15 in: s15\n} } } */
-/* { dg-final { scan-assembler {\t// s16 out: s16\n.*\tfmov\t(s[0-7]), s16\n.*[/]/ s16 in: \1\n} } } */
-/* { dg-final { scan-assembler {\t// s31 out: s31\n.*\tfmov\t(s[0-7]), s31\n.*[/]/ s31 in: \1\n} } } */
+/* { dg-final { scan-assembler {\t// s16 out: s16\n.*\tfmov\t(s[0-9]|s1[0-5]), s16\n.*[/]/ s16 in: \1\n} } } */
+/* { dg-final { scan-assembler {\t// s31 out: s31\n.*\tfmov\t(s[0-9]|s1[0-5]), s31\n.*[/]/ s31 in: \1\n} } } */
 /* { dg-final { scan-assembler-not {\t// s16 in: s16\n} } } */
 /* { dg-final { scan-assembler-not {\t// s31 in: s31\n} } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/fmul_fcvt_2.c b/gcc/testsuite/gcc.target/aarch64/fmul_fcvt_2.c
index 8f0240bf5f7585b3098ddb23fef981270b0d7c73..6cb269cf7aece4cdca43ce531c697efb1e11ec99 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/fmul_fcvt_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/fmul_fcvt_2.c
@@ -64,6 +64,6 @@ main (void)
 }
 
 /* { dg-final { scan-assembler-not "fmul\tv\[0-9\]*.*" } } */
-/* { dg-final { scan-assembler-times "fcvtzs\tv\[0-9\].4s, v\[0-9\].4s*.*#2" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtzs\tv\[0-9\].4s, v\[0-9\].4s*.*#3" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtzs\tv\[0-9\].4s, v\[0-9\].4s*.*#4" 1 } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tv\[0-9\]+.4s, v\[0-9\]+.4s*.*#2" 1 } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tv\[0-9\]+.4s, v\[0-9\]+.4s*.*#3" 1 } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tv\[0-9\]+.4s, v\[0-9\]+.4s*.*#4" 1 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/ldp_stp_17.c b/gcc/testsuite/gcc.target/aarch64/ldp_stp_17.c
index c1122fc07d5ba32b5b4d9b07eead044506084379..9260ada2aa513339f677c01eab3daba77f4a091a 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/ldp_stp_17.c
+++ b/gcc/testsuite/gcc.target/aarch64/ldp_stp_17.c
@@ -42,7 +42,7 @@ DUP_FN (8, int64_t);
 
 /*
 ** dup_16_int64_t:
-**     dup     v([0-9])\.2d, x1
+**     dup     v([0-9]+)\.2d, x1
 **     stp     q\1, q\1, \[x0\]
 **     stp     q\1, q\1, \[x0, #?32\]
 **     stp     q\1, q\1, \[x0, #?64\]

diff --git a/gcc/testsuite/gcc.target/aarch64/ldp_stp_21.c b/gcc/testsuite/gcc.target/aarch64/ldp_stp_21.c
index 462e3c9aabfb8e78e59f9a9c7fe0508a15042a4d..d54c322ce860688de734721718a9c57185d4be63 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/ldp_stp_21.c
+++ b/gcc/testsuite/gcc.target/aarch64/ldp_stp_21.c
@@ -4,4 +4,4 @@
 
 #include "ldp_stp_8.c"
 
-/* { dg-final { scan-assembler-times "ldp\td\[0-9\], d\[0-9\]+, \\\[x\[0-9\]+\\\]" 2 } } */
+/* { dg-final { scan-assembler-times "ldp\td\[0-9\]+, d\[0-9\]+, \\\[x\[0-9\]+\\\]" 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/ldp_stp_8.c b/gcc/testsuite/gcc.target/aarch64/ldp_stp_8.c
index 2d9cb6b19d563a7e1bb11c174f6d642291260f29..b25678323b85046d4a320d534be24aee429274b8 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/ldp_stp_8.c
+++ b/gcc/testsuite/gcc.target/aarch64/ldp_stp_8.c
@@ -27,4 +27,4 @@ void ldp2 (fvec *a, ivec *b, struct vec_pair *p)
   *b = p->b;
 }
 
-/* { dg-final { scan-assembler-times "ldp\td\[0-9\], d\[0-9\]+, \\\[x\[0-9\]+\\\]" 2 } } */
+/* { dg-final { scan-assembler-times "ldp\td\[0-9\]+, d\[0-9\]+, \\\[x\[0-9\]+\\\]" 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_f64.c b/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_f64.c
index 4e7aaa554b20e8d5a907041a057796d5136c7983..9155a0c8d18e13fc994bcf971aa8b1ef62a1e4d8 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_f64.c
@@ -23,4 +23,4 @@ main (void)
   return 0;
 }
 
-/* { dg-final { scan-assembler "faddp\[ \t\]+\[dD\]\[0-9\]+, v\[0-9\].2d+\n" } } */
+/* { dg-final { scan-assembler "faddp\[ \t\]+\[dD\]\[0-9\]+, v\[0-9\]+.2d+\n" } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_s64.c b/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_s64.c
index 7fe8c0643d55146863a531a6b8d7f3506fb4fd57..18d5d75fc91078406220eee9db2f208568109cd8 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_s64.c
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_s64.c
@@ -23,4 +23,4 @@ main (void)
   return 0;
 }
 
-/* { dg-final { scan-assembler "addp\[ \t\]+\[dD\]\[0-9\]+, v\[0-9\].2d+\n" } } */
+/* { dg-final { scan-assembler "addp\[ \t\]+\[dD\]\[0-9\]+, v\[0-9\]+.2d+\n" } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_u64.c b/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_u64.c
index 3f5c701ee15402810a1379908a198b3249ada3f9..c4eee61df315131f0f64c56889b185d58e142e99 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_u64.c
+++ b/gcc/testsuite/gcc.target/aarch64/simd/vpaddd_u64.c
@@ -23,4 +23,4 @@ main (void)
   return 0;
 }
 
-/* { dg-final { scan-assembler "addp\[ \t\]+\[dD\]\[0-9\]+, v\[0-9\].2d+\n" } } */
+/* { dg-final { scan-assembler "addp\[ \t\]+\[dD\]\[0-9\]+, v\[0-9\]+.2d+\n" } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/adr_1.c b/gcc/testsuite/gcc.target/aarch64/sve/adr_1.c
index 223351c2fc5683c776bd2230a938c32b73f4ff98..ff477685a01c7e7b4d91300f45a09bcca1bb19fd 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/adr_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/adr_1.c
@@ -29,18 +29,18 @@
 
 TEST_ALL (LOOP)
 
-/* { dg-final { scan-assembler-times {\tadd\tz[0-9]\.b,} 2 } } */
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]\.b,} 2 } } */
-/* { dg-final { scan-assembler-not {\tadr\tz[0-9]\.b,} } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.b,} 2 } } */
+/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b,} 2 } } */
+/* { dg-final { scan-assembler-not {\tadr\tz[0-9]+\.b,} } } */
 
-/* { dg-final { scan-assembler-times {\tadd\tz[0-9]\.h,} 2 } } */
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]\.h,} 2 } } */
-/* { dg-final { scan-assembler-not {\tadr\tz[0-9]\.h,} } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.h,} 2 } } */
+/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h,} 2 } } */
+/* { dg-final { scan-assembler-not {\tadr\tz[0-9]+\.h,} } } */
 
-/* { dg-final { scan-assembler-not {\tadd\tz[0-9]\.s,} } } */
-/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]\.s,} } } */
-/* { dg-final { scan-assembler-times {\tadr\tz[0-9]\.s, \[z[0-9]\.s, z[0-9]\.s, lsl 1\]} 2 } } */
+/* { dg-final { scan-assembler-not {\tadd\tz[0-9]+\.s,} } } */
+/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]+\.s,} } } */
+/* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.s, \[z[0-9]+\.s, z[0-9]+\.s, lsl 1\]} 2 } } */
 
-/* { dg-final { scan-assembler-not {\tadd\tz[0-9]\.d,} } } */
-/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]\.d,} } } */
-/* { dg-final { scan-assembler-times {\tadr\tz[0-9]\.d, \[z[0-9]\.d, z[0-9]\.d, lsl 1\]} 2 } } */
+/* { dg-final { scan-assembler-not {\tadd\tz[0-9]+\.d,} } } */
+/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]+\.d,} } } */
+/* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.d, \[z[0-9]+\.d, z[0-9]+\.d, lsl 1\]} 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/adr_2.c b/gcc/testsuite/gcc.target/aarch64/sve/adr_2.c
index dc20ddbad009e5dfeedcd82a1c5c41dce3c465d0..7ca1dbcb56569e48dd08f030c66180ef37a7fd91 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/adr_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/adr_2.c
@@ -4,18 +4,18 @@
 #define FACTOR 4
 #include "adr_1.c"
 
-/* { dg-final { scan-assembler-times {\tadd\tz[0-9]\.b,} 2 } } */
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]\.b,} 2 } } */
-/* { dg-final { scan-assembler-not {\tadr\tz[0-9]\.b,} } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.b,} 2 } } */
+/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b,} 2 } } */
+/* { dg-final { scan-assembler-not {\tadr\tz[0-9]+\.b,} } } */
 
-/* { dg-final { scan-assembler-times {\tadd\tz[0-9]\.h,} 2 } } */
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]\.h,} 2 } } */
-/* { dg-final { scan-assembler-not {\tadr\tz[0-9]\.h,} } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.h,} 2 } } */
+/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h,} 2 } } */
+/* { dg-final { scan-assembler-not {\tadr\tz[0-9]+\.h,} } } */
 
-/* { dg-final { scan-assembler-not {\tadd\tz[0-9]\.s,} } } */
-/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]\.s,} } } */
-/* { dg-final { scan-assembler-times {\tadr\tz[0-9]\.s, \[z[0-9]\.s, z[0-9]\.s, lsl 2\]} 2 } } */
+/* { dg-final { scan-assembler-not {\tadd\tz[0-9]+\.s,} } } */
+/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]+\.s,} } } */
+/* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.s, \[z[0-9]+\.s, z[0-9]+\.s, lsl 2\]} 2 } } */
 
-/* { dg-final { scan-assembler-not {\tadd\tz[0-9]\.d,} } } */
-/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]\.d,} } } */
-/* { dg-final { scan-assembler-times {\tadr\tz[0-9]\.d, \[z[0-9]\.d, z[0-9]\.d, lsl 2\]} 2 } } */
+/* { dg-final { scan-assembler-not {\tadd\tz[0-9]+\.d,} } } */
+/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]+\.d,} } } */
+/* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.d, \[z[0-9]+\.d, z[0-9]+\.d, lsl 2\]} 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/adr_3.c b/gcc/testsuite/gcc.target/aarch64/sve/adr_3.c
index b0cb180dde303e02d4b2246a601fc834412c55ad..da21c241a10fa3ff74c22fad53a3f1677d73f79b 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/adr_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/adr_3.c
@@ -4,18 +4,18 @@
 #define FACTOR 8
 #include "adr_1.c"
 
-/* { dg-final { scan-assembler-times {\tadd\tz[0-9]\.b,} 2 } } */
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]\.b,} 2 } } */
-/* { dg-final { scan-assembler-not {\tadr\tz[0-9]\.b,} } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.b,} 2 } } */
+/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.b,} 2 } } */
+/* { dg-final { scan-assembler-not {\tadr\tz[0-9]+\.b,} } } */
 
-/* { dg-final { scan-assembler-times {\tadd\tz[0-9]\.h,} 2 } } */
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]\.h,} 2 } } */
-/* { dg-final { scan-assembler-not {\tadr\tz[0-9]\.h,} } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.h,} 2 } } */
+/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.h,} 2 } } */
+/* { dg-final { scan-assembler-not {\tadr\tz[0-9]+\.h,} } } */
 
-/* { dg-final { scan-assembler-not {\tadd\tz[0-9]\.s,} } } */
-/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]\.s,} } } */
-/* { dg-final { scan-assembler-times {\tadr\tz[0-9]\.s, \[z[0-9]\.s, z[0-9]\.s, lsl 3\]} 2 } } */
+/* { dg-final { scan-assembler-not {\tadd\tz[0-9]+\.s,} } } */
+/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]+\.s,} } } */
+/* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.s, \[z[0-9]+\.s, z[0-9]+\.s, lsl 3\]} 2 } } */
 
-/* { dg-final { scan-assembler-not {\tadd\tz[0-9]\.d,} } } */
-/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]\.d,} } } */
-/* { dg-final { scan-assembler-times {\tadr\tz[0-9]\.d, \[z[0-9]\.d, z[0-9]\.d, lsl 3\]} 2 } } */
+/* { dg-final { scan-assembler-not {\tadd\tz[0-9]+\.d,} } } */
+/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]+\.d,} } } */
+/* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.d, \[z[0-9]+\.d, z[0-9]+\.d, lsl 3\]} 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/adr_4.c b/gcc/testsuite/gcc.target/aarch64/sve/adr_4.c
index 7c039ba1380298a0898fc5eddf9ab74d306ad222..23778983ee0d18535f7212ba862a065bdb4a049c 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/adr_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/adr_4.c
@@ -4,6 +4,6 @@
 #define FACTOR 16
 #include "adr_1.c"
 
-/* { dg-final { scan-assembler-times {\tadd\tz[0-9]\.[bhsd],} 8 } } */
-/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]\.[bhsd],} 8 } } */
-/* { dg-final { scan-assembler-not {\tadr\tz[0-9]\.[bhsd],} } } */
+/* { dg-final { scan-assembler-times {\tadd\tz[0-9]+\.[bhsd],} 8 } } */
+/* { dg-final { scan-assembler-times {\tlsl\tz[0-9]+\.[bhsd],} 8 } } */
+/* { dg-final { scan-assembler-not {\tadr\tz[0-9]+\.[bhsd],} } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/adr_5.c b/gcc/testsuite/gcc.target/aarch64/sve/adr_5.c
index ce3991cb2e5c2c1270eaa2a6c300fa8ed16c7e27..62806825216a472121061f43618777fb8d10a275 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/adr_5.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/adr_5.c
@@ -17,11 +17,11 @@
 
 TEST_ALL (LOOP)
 
-/* { dg-final { scan-assembler-not {\tadd\tz[0-9]\.d,} } } */
-/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]\.d,} } } */
-/* { dg-final { scan-assembler-not {\tand\tz[0-9]\.d,} } } */
-/* { dg-final { scan-assembler-not {\tuxtw\tz[0-9]\.d,} } } */
-/* { dg-final { scan-assembler-times {\tadr\tz[0-9]\.d, \[z[0-9]\.d, z[0-9]\.d, uxtw\]} 1 } } */
-/* { dg-final { scan-assembler-times {\tadr\tz[0-9]\.d, \[z[0-9]\.d, z[0-9]\.d, uxtw 1\]} 1 } } */
-/* { dg-final { scan-assembler-times {\tadr\tz[0-9]\.d, \[z[0-9]\.d, z[0-9]\.d, uxtw 2\]} 1 } } */
-/* { dg-final { scan-assembler-times {\tadr\tz[0-9]\.d, \[z[0-9]\.d, z[0-9]\.d, uxtw 3\]} 1 } } */
+/* { dg-final { scan-assembler-not {\tadd\tz[0-9]+\.d,} } } */
+/* { dg-final { scan-assembler-not {\tlsl\tz[0-9]+\.d,} } } */
+/* { dg-final { scan-assembler-not {\tand\tz[0-9]+\.d,} } } */
+/* { dg-final { scan-assembler-not {\tuxtw\tz[0-9]+\.d,} } } */
+/* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.d, \[z[0-9]+\.d, z[0-9]+\.d, uxtw\]} 1 } } */
+/* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.d, \[z[0-9]+\.d, z[0-9]+\.d, uxtw 1\]} 1 } } */
+/* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.d, \[z[0-9]+\.d, z[0-9]+\.d, uxtw 2\]} 1 } } */
+/* { dg-final { scan-assembler-times {\tadr\tz[0-9]+\.d, \[z[0-9]+\.d, z[0-9]+\.d, uxtw 3\]} 1 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/extract_1.c b/gcc/testsuite/gcc.target/aarch64/sve/extract_1.c
index dbcc1d943e1b29f5dd0482c442146394931828a4..5d5edf26c19ca0b6595d25ae9d3a4f7de0686195 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/extract_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/extract_1.c
@@ -56,7 +56,7 @@ typedef _Float16 vnx8hf __attribute__((vector_size (32)));
 
 TEST_ALL (EXTRACT)
 
-/* { dg-final { scan-assembler-times {\tfmov\tx[0-9]+, d[0-9]\n} 2 { target aarch64_little_endian } } } */
+/* { dg-final { scan-assembler-times {\tfmov\tx[0-9]+, d[0-9]+\n} 2 { target aarch64_little_endian } } } */
 /* { dg-final { scan-assembler-times {\tumov\tx[0-9]+, v[0-9]+\.d\[0\]\n} 1 { target aarch64_big_endian } } } */
 /* { dg-final { scan-assembler-times {\tumov\tx[0-9]+, v[0-9]+\.d\[1\]\n} 1 } } */
 /* { dg-final { scan-assembler-not {\tdup\td[0-9]+, v[0-9]+\.d\[0\]\n} } } */
@@ -65,7 +65,7 @@ TEST_ALL (EXTRACT)
 /* { dg-final { scan-assembler-times {\tlastb\tx[0-9]+, p[0-7], z[0-9]+\.d\n} 1 } } */
 /* { dg-final { scan-assembler-times {\tlastb\td[0-9]+, p[0-7], z[0-9]+\.d\n} 1 } } */
 
-/* { dg-final { scan-assembler-times {\tfmov\tw[0-9]+, s[0-9]\n} 2 { target aarch64_little_endian } } } */
+/* { dg-final { scan-assembler-times {\tfmov\tw[0-9]+, s[0-9]+\n} 2 { target aarch64_little_endian } } } */
 /* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[0\]\n} 1 { target aarch64_big_endian } } } */
 /* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[1\]\n} 1 } } */
 /* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[3\]\n} 1 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/extract_2.c b/gcc/testsuite/gcc.target/aarch64/sve/extract_2.c
index a48774664dd270a96da755ac5f8be22fc6680b30..0e6ec836228018ed836c08b6a9af17ec5ac69962 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/extract_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/extract_2.c
@@ -56,7 +56,7 @@ typedef _Float16 vnx16hf __attribute__((vector_size (64)));
 
 TEST_ALL (EXTRACT)
 
-/* { dg-final { scan-assembler-times {\tfmov\tx[0-9]+, d[0-9]\n} 2 { target aarch64_little_endian } } } */
+/* { dg-final { scan-assembler-times {\tfmov\tx[0-9]+, d[0-9]+\n} 2 { target aarch64_little_endian } } } */
 /* { dg-final { scan-assembler-times {\tumov\tx[0-9]+, v[0-9]+\.d\[0\]\n} 1 { target aarch64_big_endian } } } */
 /* { dg-final { scan-assembler-times {\tumov\tx[0-9]+, v[0-9]+\.d\[1\]\n} 1 } } */
 /* { dg-final { scan-assembler-not {\tdup\td[0-9]+, v[0-9]+\.d\[0\]\n} } } */
@@ -65,7 +65,7 @@ TEST_ALL (EXTRACT)
 /* { dg-final { scan-assembler-times {\tlastb\tx[0-9]+, p[0-7], z[0-9]+\.d\n} 1 } } */
 /* { dg-final { scan-assembler-times {\tlastb\td[0-9]+, p[0-7], z[0-9]+\.d\n} 1 } } */
 
-/* { dg-final { scan-assembler-times {\tfmov\tw[0-9]+, s[0-9]\n} 2 { target aarch64_little_endian } } } */
+/* { dg-final { scan-assembler-times {\tfmov\tw[0-9]+, s[0-9]+\n} 2 { target aarch64_little_endian } } } */
 /* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[0\]\n} 1 { target aarch64_big_endian } } } */
 /* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[1\]\n} 1 } } */
 /* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[3\]\n} 1 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/extract_3.c b/gcc/testsuite/gcc.target/aarch64/sve/extract_3.c
index bf10bf16efd9452269f219b5daa29b720d50532e..0d7a2fa2527a194a7cf0014db17ea4c68a76e99e 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/extract_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/extract_3.c
@@ -77,7 +77,7 @@ typedef _Float16 vnx32hf __attribute__((vector_size (128)));
 
 TEST_ALL (EXTRACT)
 
-/* { dg-final { scan-assembler-times {\tfmov\tx[0-9]+, d[0-9]\n} 5 { target aarch64_little_endian } } } */
+/* { dg-final { scan-assembler-times {\tfmov\tx[0-9]+, d[0-9]+\n} 5 { target aarch64_little_endian } } } */
 /* { dg-final { scan-assembler-times {\tumov\tx[0-9]+, v[0-9]+\.d\[0\]\n} 1 { target aarch64_big_endian } } } */
 /* { dg-final { scan-assembler-times {\tumov\tx[0-9]+, v[0-9]+\.d\[1\]\n} 1 } } */
 /* { dg-final { scan-assembler-not {\tdup\td[0-9]+, v[0-9]+\.d\[0\]\n} } } */
@@ -87,7 +87,7 @@ TEST_ALL (EXTRACT)
 /* { dg-final { scan-assembler-times {\tlastb\tx[0-9]+, p[0-7], z[0-9]+\.d\n} 1 } } */
 /* { dg-final { scan-assembler-times {\tlastb\td[0-9]+, p[0-7], z[0-9]+\.d\n} 1 } } */
 
-/* { dg-final { scan-assembler-times {\tfmov\tw[0-9]+, s[0-9]\n} 5 { target aarch64_little_endian } } } */
+/* { dg-final { scan-assembler-times {\tfmov\tw[0-9]+, s[0-9]+\n} 5 { target aarch64_little_endian } } } */
 /* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[0\]\n} 1 { target aarch64_big_endian } } } */
 /* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[1\]\n} 1 } } */
 /* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[3\]\n} 1 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/extract_4.c b/gcc/testsuite/gcc.target/aarch64/sve/extract_4.c
index 9805678c12ee7d2ba1af0faf0e0c46a72f14d5cd..a706291023f4bd3f190e0880fd94932108488c6e 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/extract_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/extract_4.c
@@ -84,7 +84,7 @@ typedef _Float16 v128hf __attribute__((vector_size (256)));
 
 TEST_ALL (EXTRACT)
 
-/* { dg-final { scan-assembler-times {\tfmov\tx[0-9]+, d[0-9]\n} 6 { target aarch64_little_endian } } } */
+/* { dg-final { scan-assembler-times {\tfmov\tx[0-9]+, d[0-9]+\n} 6 { target aarch64_little_endian } } } */
 /* { dg-final { scan-assembler-times {\tumov\tx[0-9]+, v[0-9]+\.d\[0\]\n} 1 { target aarch64_big_endian } } } */
 /* { dg-final { scan-assembler-times {\tumov\tx[0-9]+, v[0-9]+\.d\[1\]\n} 1 } } */
 /* { dg-final { scan-assembler-not {\tdup\td[0-9]+, v[0-9]+\.d\[0\]\n} } } */
@@ -94,7 +94,7 @@ TEST_ALL (EXTRACT)
 /* { dg-final { scan-assembler-times {\tlastb\tx[0-9]+, p[0-7], z[0-9]+\.d\n} 1 } } */
 /* { dg-final { scan-assembler-times {\tlastb\td[0-9]+, p[0-7], z[0-9]+\.d\n} 1 } } */
 
-/* { dg-final { scan-assembler-times {\tfmov\tw[0-9]+, s[0-9]\n} 6 { target aarch64_little_endian } } } */
+/* { dg-final { scan-assembler-times {\tfmov\tw[0-9]+, s[0-9]+\n} 6 { target aarch64_little_endian } } } */
 /* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[0\]\n} 1 { target aarch64_big_endian } } } */
 /* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[1\]\n} 1 } } */
 /* { dg-final { scan-assembler-times {\tumov\tw[0-9]+, v[0-9]+\.s\[3\]\n} 1 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_9.c b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_9.c
index ad32e1fe56dde46c586e20cd7dc037944556156c..3b2604e6068459cfdb9f4fa1f5f8440f11476025 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_9.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/pcs/return_9.c
@@ -22,7 +22,7 @@ callee_s8 (void)
 ** caller_s8:
 **     ...
 **     bl      callee_s8
-**     add     (z[2-7]\.b), z2\.b, z3\.b
+**     add     (z(?:[2-7]|2[4-9]|3[01])\.b), z2\.b, z3\.b
 **     ptrue   (p[0-7])\.b, all
 **     mla     z0\.b, \2/m, (z1\.b, \1|\1, z1\.b)
 **     ldp     x29, x30, \[sp\], 16
@@ -57,7 +57,7 @@ callee_u8 (void)
 ** caller_u8:
 **     ...
 **     bl      callee_u8
-**     sub     (z[2-7]\.b), z2\.b, z3\.b
+**     sub     (z(?:[2-7]|2[4-9]|3[01])\.b), z2\.b, z3\.b
 **     ptrue   (p[0-7])\.b, all
 **     mla     z0\.b, \2/m, (z1\.b, \1|\1, z1\.b)
 **     ldp     x29, x30, \[sp\], 16
@@ -93,7 +93,7 @@ callee_s16 (void)
 ** caller_s16:
 **     ...
 **     bl      callee_s16
-**     add     (z[2-7]\.h), z2\.h, z3\.h
+**     add     (z(?:[2-7]|2[4-9]|3[01])\.h), z2\.h, z3\.h
 **     ptrue   (p[0-7])\.b, all
 **     mad     z0\.h, \2/m, (z1\.h, \1|\1, z1\.h)
 **     ldp     x29, x30, \[sp\], 16
@@ -129,7 +129,7 @@ callee_u16 (void)
 ** caller_u16:
 **     ...
 **     bl      callee_u16
-**     sub     (z[2-7]\.h), z2\.h, z3\.h
+**     sub     (z(?:[2-7]|2[4-9]|3[01])\.h), z2\.h, z3\.h
 **     ptrue   (p[0-7])\.b, all
 **     mad     z0\.h, \2/m, (z1\.h, \1|\1, z1\.h)
 **     ldp     x29, x30, \[sp\], 16
@@ -236,7 +236,7 @@ callee_s32 (void)
 ** caller_s32:
 **     ...
 **     bl      callee_s32
-**     add     (z[2-7]\.s), z2\.s, z3\.s
+**     add     (z(?:[2-7]|2[4-9]|3[01])\.s), z2\.s, z3\.s
 **     ptrue   (p[0-7])\.b, all
 **     msb     z0\.s, \2/m, (z1\.s, \1|\1, z1\.s)
 **     ldp     x29, x30, \[sp\], 16
@@ -272,7 +272,7 @@ callee_u32 (void)
 ** caller_u32:
 **     ...
 **     bl      callee_u32
-**     sub     (z[2-7]\.s), z2\.s, z3\.s
+**     sub     (z(?:[2-7]|2[4-9]|3[01])\.s), z2\.s, z3\.s
 **     ptrue   (p[0-7])\.b, all
 **     msb     z0\.s, \2/m, (z1\.s, \1|\1, z1\.s)
 **     ldp     x29, x30, \[sp\], 16
@@ -346,7 +346,7 @@ callee_s64 (void)
 ** caller_s64:
 **     ...
 **     bl      callee_s64
-**     add     (z[2-7]\.d), z2\.d, z3\.d
+**     add     (z(?:[2-7]|2[4-9]|3[01])\.d), z2\.d, z3\.d
 **     ptrue   (p[0-7])\.b, all
 **     mls     z0\.d, \2/m, (z1\.d, \1|\1, z1\.d)
 **     ldp     x29, x30, \[sp\], 16
@@ -382,7 +382,7 @@ callee_u64 (void)
 ** caller_u64:
 **     ...
 **     bl      callee_u64
-**     sub     (z[2-7]\.d), z2\.d, z3\.d
+**     sub     (z(?:[2-7]|2[4-9]|3[01])\.d), z2\.d, z3\.d
 **     ptrue   (p[0-7])\.b, all
 **     mls     z0\.d, \2/m, (z1\.d, \1|\1, z1\.d)
 **     ldp     x29, x30, \[sp\], 16

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/slp_4.c b/gcc/testsuite/gcc.target/aarch64/sve/slp_4.c
index 49fb828e874f05d6448325780084f9cfb253fc01..b1fa5e3cf68ba5dfcde0052a72cc1f98e3592426 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/slp_4.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/slp_4.c
@@ -38,7 +38,7 @@ TEST_ALL (VEC_PERM)
 /* 1 for each 8-bit type, 4 for each 32-bit type and 4 for double.  */
 /* { dg-final { scan-assembler-times {\tld1rd\tz[0-9]+\.d, } 18 } } */
 /* 1 for each 16-bit type.  */
-/* { dg-final { scan-assembler-times {\tld1rqh\tz[0-9]\.h, } 3 } } */
+/* { dg-final { scan-assembler-times {\tld1rqh\tz[0-9]+\.h, } 3 } } */
 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #99\n} 2 } } */
 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #11\n} 2 } } */
 /* { dg-final { scan-assembler-times {\tmov\tz[0-9]+\.d, #17\n} 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/spill_3.c b/gcc/testsuite/gcc.target/aarch64/sve/spill_3.c
index 8cb904ed0fb9caad6fcdce5f8658f23aed79d869..b90cdb948e3d894e7e13dfe39b7b73d51272169f 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/sve/spill_3.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/spill_3.c
@@ -38,10 +38,10 @@ TEST_LOOP (uint32_t);
 /* Four iterations are needed; ought to stay a loop.  */
 TEST_LOOP (uint64_t);
 
-/* { dg-final { scan-assembler {\tld1b\tz[0-9]\.b} } } */
-/* { dg-final { scan-assembler {\tld1h\tz[0-9]\.h} } } */
-/* { dg-final { scan-assembler {\tld1w\tz[0-9]\.s} } } */
-/* { dg-final { scan-assembler {\tld1d\tz[0-9]\.d} } } */
+/* { dg-final { scan-assembler {\tld1b\tz[0-9]+\.b} } } */
+/* { dg-final { scan-assembler {\tld1h\tz[0-9]+\.h} } } */
+/* { dg-final { scan-assembler {\tld1w\tz[0-9]+\.s} } } */
+/* { dg-final { scan-assembler {\tld1d\tz[0-9]+\.d} } } */
 /* { dg-final { scan-assembler-not {\tldr\tz[0-9]} } } */
 /* { dg-final { scan-assembler-not {\tstr\tz[0-9]} } } */
 /* { dg-final { scan-assembler-not {\tldr\tp[0-9]} } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/vfp-1.c b/gcc/testsuite/gcc.target/aarch64/vfp-1.c
index 02609bb52bafd43803be29cf15225568f7713434..9bd7d161b1f3b659580a12dd253cc641767f0ca7 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/vfp-1.c
+++ b/gcc/testsuite/gcc.target/aarch64/vfp-1.c
@@ -82,13 +82,13 @@ void test_convert () {
   /* { dg-final { scan-assembler "fcvt\ts\[0-9\]*" } } */
   f1 = d1;
   /* fixsfsi2 */
-  /* { dg-final { scan-assembler "fcvtzs\ts\[0-9\], s\[0-9\]*" } } */
+  /* { dg-final { scan-assembler "fcvtzs\ts\[0-9\]+, s\[0-9\]*" } } */
   i1 = f1;
   /* fixdfsi2 */
   /* { dg-final { scan-assembler "fcvtzs\tw\[0-9\], d\[0-9\]*" } } */
   i1 = d1;
   /* fixunsfsi2 */
-  /* { dg-final { scan-assembler "fcvtzu\ts\[0-9\], s\[0-9\]*" } } */
+  /* { dg-final { scan-assembler "fcvtzu\ts\[0-9\]+, s\[0-9\]*" } } */
   u1 = f1;
   /* fixunsdfsi2 */
   /* { dg-final { scan-assembler "fcvtzu\tw\[0-9\], d\[0-9\]*" } } */