]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
arm64: dts: renesas: r9a07g0{43,44,54}: Remove TCIU8 interrupt from MTU3
authorCosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Fri, 10 Apr 2026 16:35:28 +0000 (19:35 +0300)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Sun, 31 May 2026 08:39:32 +0000 (10:39 +0200)
The TCIU8 interrupt used to be documented in earlier revisions of the
user manuals, but has since been removed.  The corresponding entry is
now marked as reserved in the interrupt mapping tables of all supported
SoCs.

  - Page 486, Table 8.2 Interrupt mapping (7/13) in the Renesas RZ/G2UL
    Rev.1.40 User Manual
  - Page 363, Table 8.2 Interrupt Mapping (6/13) in the Renesas RZ/Five
    Rev.1.30 User Manual
  - Page 528, Table 8.2 Interrupt mapping (7/13) in the Renesas RZ/G2L
    and RZ/G2LC Rev.1.50 User Manual
  - Page 540, Table 8.2 Interrupt mapping (7/13) in the Renesas RZ/V2L
    Rev.1.50 User Manual

Remove the TCIU8 interrupt.  This does not cause any breakage as the
driver does not make use of the interrupts.

Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260410163530.383818-9-cosmin-gabriel.tanislav.xa@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
arch/arm64/boot/dts/renesas/r9a07g043.dtsi
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
arch/arm64/boot/dts/renesas/r9a07g054.dtsi

index ded4f1f11d6052fe14c7bbb4c6aab349b32f0b7f..38aebeeea46460d16aa5e6d2bbe1090c314c9665 100644 (file)
                                     <SOC_PERIPHERAL_IRQ(209) IRQ_TYPE_EDGE_RISING>,
                                     <SOC_PERIPHERAL_IRQ(210) IRQ_TYPE_EDGE_RISING>,
                                     <SOC_PERIPHERAL_IRQ(211) IRQ_TYPE_EDGE_RISING>,
-                                    <SOC_PERIPHERAL_IRQ(212) IRQ_TYPE_EDGE_RISING>,
-                                    <SOC_PERIPHERAL_IRQ(213) IRQ_TYPE_EDGE_RISING>;
+                                    <SOC_PERIPHERAL_IRQ(212) IRQ_TYPE_EDGE_RISING>;
                        interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
                                          "tciv0", "tgie0", "tgif0",
                                          "tgia1", "tgib1", "tciv1", "tciu1",
                                          "tgia7", "tgib7", "tgic7", "tgid7",
                                          "tciv7",
                                          "tgia8", "tgib8", "tgic8", "tgid8",
-                                         "tciv8", "tciu8";
+                                         "tciv8";
                        clocks = <&cpg CPG_MOD R9A07G043_MTU_X_MCK_MTU3>;
                        power-domains = <&cpg>;
                        resets = <&cpg R9A07G043_MTU_X_PRESET_MTU3>;
index cb0c9550aa0334eed808ebc3417f493eb6b2f6a0..873b52b168bc793445d51330d9462a890bd1b666 100644 (file)
                                     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
                                     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
                                     <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
-                                    <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
-                                    <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
+                                    <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>;
                        interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
                                          "tciv0", "tgie0", "tgif0",
                                          "tgia1", "tgib1", "tciv1", "tciu1",
                                          "tgia7", "tgib7", "tgic7", "tgid7",
                                          "tciv7",
                                          "tgia8", "tgib8", "tgic8", "tgid8",
-                                         "tciv8", "tciu8";
+                                         "tciv8";
                        clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
                        power-domains = <&cpg>;
                        resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
index 7a3e5b6a685f54740419b3e1f166401de78299bc..587fab0ceb3fa7e695d643d242c4ba80f7ef7ecc 100644 (file)
                                     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
                                     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
                                     <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
-                                    <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
-                                    <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
+                                    <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>;
                        interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
                                          "tciv0", "tgie0", "tgif0",
                                          "tgia1", "tgib1", "tciv1", "tciu1",
                                          "tgia7", "tgib7", "tgic7", "tgid7",
                                          "tciv7",
                                          "tgia8", "tgib8", "tgic8", "tgid8",
-                                         "tciv8", "tciu8";
+                                         "tciv8";
                        clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>;
                        power-domains = <&cpg>;
                        resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>;