Support XCHG AX, reg16 on amd64. Fixes #252695.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2191

diff --git a/VEX/priv/guest_amd64_toIR.c b/VEX/priv/guest_amd64_toIR.c
index 42345371b3276d16064750187470678aedc8a5ad..55182dd5995ed83c433f77c9e509e4425bff2cf5 100644 (file)
--- a/VEX/priv/guest_amd64_toIR.c
+++ b/VEX/priv/guest_amd64_toIR.c
@@ -1104,6 +1104,13 @@ static IRExpr* getIReg16 ( UInt regno )
                       Ity_I16 );
 }
 
+static void putIReg16 ( UInt regno, IRExpr* e )
+{
+   vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I16);
+   stmt( IRStmt_Put( integerGuestReg64Offset(regno), 
+                     unop(Iop_16Uto64,e) ) );
+}
+
 static HChar* nameIReg16 ( UInt regno )
 {
    return nameIReg( 2, regno, False );
@@ -7629,18 +7636,23 @@ void codegen_xchg_rAX_Reg ( Prefix pfx, Int sz, UInt regLo3 )
    IRType ty = szToITy(sz);
    IRTemp t1 = newTemp(ty);
    IRTemp t2 = newTemp(ty);
-   vassert(sz == 4 || sz == 8);
+   vassert(sz == 2 || sz == 4 || sz == 8);
    vassert(regLo3 < 8);
    if (sz == 8) {
       assign( t1, getIReg64(R_RAX) );
       assign( t2, getIRegRexB(8, pfx, regLo3) );
       putIReg64( R_RAX, mkexpr(t2) );
       putIRegRexB(8, pfx, regLo3, mkexpr(t1) );
-   } else {
+   } else if (sz == 4) {
       assign( t1, getIReg32(R_RAX) );
       assign( t2, getIRegRexB(4, pfx, regLo3) );
       putIReg32( R_RAX, mkexpr(t2) );
       putIRegRexB(4, pfx, regLo3, mkexpr(t1) );
+   } else {
+      assign( t1, getIReg16(R_RAX) );
+      assign( t2, getIRegRexB(2, pfx, regLo3) );
+      putIReg16( R_RAX, mkexpr(t2) );
+      putIRegRexB(2, pfx, regLo3, mkexpr(t1) );
    }
    DIP("xchg%c %s, %s\n", 
        nameISize(sz), nameIRegRAX(sz), 
@@ -17527,9 +17539,6 @@ DisResult disInstr_AMD64_WRK (
       /* guard against mutancy */
       if (haveF2orF3(pfx)) goto decode_failure;
 
-      /* sz == 2 could legitimately happen, but we don't handle it yet */
-      if (sz == 2) goto decode_failure; /* awaiting test case */
-
       codegen_xchg_rAX_Reg ( pfx, sz, opc - 0x90 );
       break;