clk: nxp: Fix pll0 rate check condition in LPC18xx CGU driver

[ Upstream commit 1624dead9a4d288a594fdf19735ebfe4bb567cb8 ]

The conditional check for the PLL0 multiplier 'm' used a logical AND
instead of OR, making the range check ineffective. This patch replaces
&& with || to correctly reject invalid values of 'm' that are either
less than or equal to 0 or greater than LPC18XX_PLL0_MSEL_MAX.

This ensures proper bounds checking during clk rate setting and rounding.

Fixes: b04e0b8fd544 ("clk: add lpc18xx cgu clk driver")
Signed-off-by: Alok Tiwari <alok.a.tiwari@oracle.com>
[sboyd@kernel.org: 'm' is unsigned so remove < condition]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/nxp/clk-lpc18xx-cgu.c b/drivers/clk/nxp/clk-lpc18xx-cgu.c
index 821155f79b0155139806a922f10d5a71a7ff9b51..bbd7d64038fab53301c43fabc933d89dd555462c 100644 (file)
--- a/drivers/clk/nxp/clk-lpc18xx-cgu.c
+++ b/drivers/clk/nxp/clk-lpc18xx-cgu.c
@@ -382,7 +382,7 @@ static int lpc18xx_pll0_determine_rate(struct clk_hw *hw,
        }
 
        m = DIV_ROUND_UP_ULL(req->best_parent_rate, req->rate * 2);
-       if (m <= 0 && m > LPC18XX_PLL0_MSEL_MAX) {
+       if (m == 0 || m > LPC18XX_PLL0_MSEL_MAX) {
                pr_warn("%s: unable to support rate %lu\n", __func__, req->rate);
                return -EINVAL;
        }
@@ -405,7 +405,7 @@ static int lpc18xx_pll0_set_rate(struct clk_hw *hw, unsigned long rate,
        }
 
        m = DIV_ROUND_UP_ULL(parent_rate, rate * 2);
-       if (m <= 0 && m > LPC18XX_PLL0_MSEL_MAX) {
+       if (m == 0 || m > LPC18XX_PLL0_MSEL_MAX) {
                pr_warn("%s: unable to support rate %lu\n", __func__, rate);
                return -EINVAL;
        }