arm64: dts: rockchip: Fix rk356x PCIe register and range mappings

commit 568a67e742dfa90b19a23305317164c5c350b71e upstream.

The register and range mappings for the PCIe controller in Rockchip's
RK356x SoCs are incorrect. Replace them with corrected values from the
vendor BSP sources, updated to match current DT schema.

These values are also used in u-boot.

Fixes: 66b51ea7d70f ("arm64: dts: rockchip: Add rk3568 PCIe2x1 controller")
Cc: stable@vger.kernel.org
Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
Tested-by: Diederik de Haas <didi.debian@cknow.org>
Link: https://lore.kernel.org/r/20230601132516.153934-1-frattaroli.nicolas@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index ba67b58f05b790c55d63427aaa87215441b6f082..f1be76a54ceb0cb0730f444c69c3da73e07194c9 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -94,9 +94,10 @@
                power-domains = <&power RK3568_PD_PIPE>;
                reg = <0x3 0xc0400000 0x0 0x00400000>,
                      <0x0 0xfe270000 0x0 0x00010000>,
-                     <0x3 0x7f000000 0x0 0x01000000>;
-               ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>,
-                        <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>;
+                     <0x0 0xf2000000 0x0 0x00100000>;
+               ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
+                        <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>,
+                        <0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>;
                reg-names = "dbi", "apb", "config";
                resets = <&cru SRST_PCIE30X1_POWERUP>;
                reset-names = "pipe";
@@ -146,9 +147,10 @@
                power-domains = <&power RK3568_PD_PIPE>;
                reg = <0x3 0xc0800000 0x0 0x00400000>,
                      <0x0 0xfe280000 0x0 0x00010000>,
-                     <0x3 0xbf000000 0x0 0x01000000>;
-               ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>,
-                        <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>;
+                     <0x0 0xf0000000 0x0 0x00100000>;
+               ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
+                        <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>,
+                        <0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>;
                reg-names = "dbi", "apb", "config";
                resets = <&cru SRST_PCIE30X2_POWERUP>;
                reset-names = "pipe";

diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index eed0059a68b8dbc8e6d3ce70b7cefffc9c2c7c3a..3ee5d764ac63e1fa4b2a5cf4d13c94cfb7900111 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -952,7 +952,7 @@
                compatible = "rockchip,rk3568-pcie";
                reg = <0x3 0xc0000000 0x0 0x00400000>,
                      <0x0 0xfe260000 0x0 0x00010000>,
-                     <0x3 0x3f000000 0x0 0x01000000>;
+                     <0x0 0xf4000000 0x0 0x00100000>;
                reg-names = "dbi", "apb", "config";
                interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
@@ -982,8 +982,9 @@
                phys = <&combphy2 PHY_TYPE_PCIE>;
                phy-names = "pcie-phy";
                power-domains = <&power RK3568_PD_PIPE>;
-               ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000
-                         0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>;
+               ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
+                        <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
+                        <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
                resets = <&cru SRST_PCIE20_POWERUP>;
                reset-names = "pipe";
                #address-cells = <3>;