arm64: dts: renesas: r9a09g087: Add ETHSS node

Add an Ethernet Switch Subsystem (ETHSS) device node to the RZ/N2H
(R9A09G087) SoC. The ETHSS IP block is responsible for handling MII
pass-through or conversion to RMII/RGMII.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251028175458.1037397-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
index 3ece794fb0a7cdf85dffa436f6c92411c358ee9f..fe0087a7d4b4e75cf60e4d7257a3d8d279034c17 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
@@ -270,6 +270,43 @@
                        status = "disabled";
                };
 
+               ethss: ethss@80110000 {
+                       compatible = "renesas,r9a09g087-miic", "renesas,r9a09g077-miic";
+                       reg =  <0 0x80110000 0 0x10000>;
+                       clocks = <&cpg CPG_CORE R9A09G087_ETCLKE>,
+                                <&cpg CPG_CORE R9A09G087_ETCLKB>,
+                                <&cpg CPG_CORE R9A09G087_ETCLKD>,
+                                <&cpg CPG_MOD 403>;
+                       clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk";
+                       resets = <&cpg 405>, <&cpg 406>;
+                       reset-names = "rst", "crst";
+                       power-domains = <&cpg>;
+                       status = "disabled";
+
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       mii_conv0: mii-conv@0 {
+                               reg = <0>;
+                               status = "disabled";
+                       };
+
+                       mii_conv1: mii-conv@1 {
+                               reg = <1>;
+                               status = "disabled";
+                       };
+
+                       mii_conv2: mii-conv@2 {
+                               reg = <2>;
+                               status = "disabled";
+                       };
+
+                       mii_conv3: mii-conv@3 {
+                               reg = <3>;
+                               status = "disabled";
+                       };
+               };
+
                cpg: clock-controller@80280000 {
                        compatible = "renesas,r9a09g087-cpg-mssr";
                        reg = <0 0x80280000 0 0x1000>,