+2009-08-28 Uros Bizjak <ubizjak@gmail.com>
+
+ Backport from mainline:
+ 2009-08-26 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/alpha/sync.md: Update comment about unpredictable LL/SC lock
+ clearing by a taken branch.
+ (sync_<fetchop_name><mode>): Split when epilogue_completed is set,
+ effectively after bbro pass.
+ (sync_nand<mode>): Ditto.
+ (sync_old_<fetchop_name><mode>): Ditto.
+ (sync_old_nand<mode>): Ditto.
+ (sync_new_<fetchop_name><mode>): Dito.
+ (sync_new_nand<mode>): Ditto.
+ (sync_compare_and_swap<mode>_1): Ditto.
+ (*sync_compare_and_swap<mode>): Ditto.
+ (sync_lock_test_and_set<mode>_1): Ditto.
+ ("sync_lock_test_and_set<mode>): Ditto.
+
+ 2009-08-25 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/alpha/alpha.md (*cmpdf_ieee_ext[123]): Remove.
+ (*cmpdf_internal): Enable for all ALPHA_FPTM levels.
+ (*movdfcc_ext[1234]): Disable for IEEE mode.
+
+ 2009-08-16 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/alpha/alpha.c (alpha_end_function): Handle NULL_RTX returned
+ from prev_active_insn.
+
2009-08-24 Richard Guenther <rguenther@suse.de>
PR middle-end/41094
insn = get_last_insn ();
if (!INSN_P (insn))
insn = prev_active_insn (insn);
- if (GET_CODE (insn) == CALL_INSN)
+ if (insn && GET_CODE (insn) == CALL_INSN)
output_asm_insn (get_insn_template (CODE_FOR_nop, NULL), NULL);
#if TARGET_ABI_OSF
(match_operator:DF 1 "alpha_fp_comparison_operator"
[(match_operand:DF 2 "reg_or_0_operand" "fG")
(match_operand:DF 3 "reg_or_0_operand" "fG")]))]
- "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
- "cmp%-%C1%/ %R2,%R3,%0"
- [(set_attr "type" "fadd")
- (set_attr "trap" "yes")
- (set_attr "trap_suffix" "su")])
-
-(define_insn "*cmpdf_ieee_ext1"
- [(set (match_operand:DF 0 "register_operand" "=&f")
- (match_operator:DF 1 "alpha_fp_comparison_operator"
- [(float_extend:DF
- (match_operand:SF 2 "reg_or_0_operand" "fG"))
- (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
- "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
+ "TARGET_FP"
"cmp%-%C1%/ %R2,%R3,%0"
[(set_attr "type" "fadd")
(set_attr "trap" "yes")
(set_attr "trap" "yes")
(set_attr "trap_suffix" "su")])
-(define_insn "*cmpdf_ieee_ext2"
- [(set (match_operand:DF 0 "register_operand" "=&f")
- (match_operator:DF 1 "alpha_fp_comparison_operator"
- [(match_operand:DF 2 "reg_or_0_operand" "fG")
- (float_extend:DF
- (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
- "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
- "cmp%-%C1%/ %R2,%R3,%0"
- [(set_attr "type" "fadd")
- (set_attr "trap" "yes")
- (set_attr "trap_suffix" "su")])
-
(define_insn "*cmpdf_ext2"
[(set (match_operand:DF 0 "register_operand" "=f")
(match_operator:DF 1 "alpha_fp_comparison_operator"
(set_attr "trap" "yes")
(set_attr "trap_suffix" "su")])
-(define_insn "*cmpdf_ieee_ext3"
- [(set (match_operand:DF 0 "register_operand" "=&f")
- (match_operator:DF 1 "alpha_fp_comparison_operator"
- [(float_extend:DF
- (match_operand:SF 2 "reg_or_0_operand" "fG"))
- (float_extend:DF
- (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
- "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
- "cmp%-%C1%/ %R2,%R3,%0"
- [(set_attr "type" "fadd")
- (set_attr "trap" "yes")
- (set_attr "trap_suffix" "su")])
-
(define_insn "*cmpdf_ext3"
[(set (match_operand:DF 0 "register_operand" "=f")
(match_operator:DF 1 "alpha_fp_comparison_operator"
(match_operand:DF 2 "const0_operand" "G,G")])
(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
(match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
- "TARGET_FP"
+ "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"@
fcmov%C3 %R4,%R1,%0
fcmov%D3 %R4,%R5,%0"
(match_operand:DF 2 "const0_operand" "G,G")])
(match_operand:DF 1 "reg_or_0_operand" "fG,0")
(match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
- "TARGET_FP"
+ "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"@
fcmov%C3 %R4,%R1,%0
fcmov%D3 %R4,%R5,%0"
(match_operand:DF 2 "const0_operand" "G,G")])
(match_operand:SF 1 "reg_or_0_operand" "fG,0")
(match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
- "TARGET_FP"
+ "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"@
fcmov%C3 %R4,%R1,%0
fcmov%D3 %R4,%R5,%0"
(match_operand:DF 2 "const0_operand" "G,G")])
(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
(match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
- "TARGET_FP"
+ "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"@
fcmov%C3 %R4,%R1,%0
fcmov%D3 %R4,%R5,%0"
[(set_attr "type" "st_c")])
;; The Alpha Architecture Handbook says that it is UNPREDICTABLE whether
-;; the lock is cleared by a TAKEN branch. If we were to honor that, it
-;; would mean that we could not expand a ll/sc sequence until after the
-;; final basic-block reordering pass. Fortunately, it appears that no
-;; Alpha implementation ever built actually clears the lock on branches,
-;; taken or not.
+;; the lock is cleared by a TAKEN branch. This means that we can not
+;; expand a ll/sc sequence until after the final basic-block reordering pass.
(define_insn_and_split "sync_<fetchop_name><mode>"
[(set (match_operand:I48MODE 0 "memory_operand" "+m")
(clobber (match_scratch:I48MODE 2 "=&r"))]
""
"#"
- "reload_completed"
+ "epilogue_completed"
[(const_int 0)]
{
alpha_split_atomic_op (<CODE>, operands[0], operands[1],
(clobber (match_scratch:I48MODE 2 "=&r"))]
""
"#"
- "reload_completed"
+ "epilogue_completed"
[(const_int 0)]
{
alpha_split_atomic_op (NOT, operands[0], operands[1],
(clobber (match_scratch:I48MODE 3 "=&r"))]
""
"#"
- "reload_completed"
+ "epilogue_completed"
[(const_int 0)]
{
alpha_split_atomic_op (<CODE>, operands[1], operands[2],
(clobber (match_scratch:I48MODE 3 "=&r"))]
""
"#"
- "reload_completed"
+ "epilogue_completed"
[(const_int 0)]
{
alpha_split_atomic_op (NOT, operands[1], operands[2],
(clobber (match_scratch:I48MODE 3 "=&r"))]
""
"#"
- "reload_completed"
+ "epilogue_completed"
[(const_int 0)]
{
alpha_split_atomic_op (<CODE>, operands[1], operands[2],
(clobber (match_scratch:I48MODE 3 "=&r"))]
""
"#"
- "reload_completed"
+ "epilogue_completed"
[(const_int 0)]
{
alpha_split_atomic_op (NOT, operands[1], operands[2],
(clobber (match_scratch:DI 6 "=X,&r"))]
""
"#"
- "reload_completed"
+ "epilogue_completed"
[(const_int 0)]
{
alpha_split_compare_and_swap_12 (<MODE>mode, operands[0], operands[1],
(clobber (match_scratch:I48MODE 4 "=&r"))]
""
"#"
- "reload_completed"
+ "epilogue_completed"
[(const_int 0)]
{
alpha_split_compare_and_swap (operands[0], operands[1], operands[2],
(clobber (match_scratch:DI 4 "=&r"))]
""
"#"
- "reload_completed"
+ "epilogue_completed"
[(const_int 0)]
{
alpha_split_lock_test_and_set_12 (<MODE>mode, operands[0], operands[1],
(clobber (match_scratch:I48MODE 3 "=&r"))]
""
"#"
- "reload_completed"
+ "epilogue_completed"
[(const_int 0)]
{
alpha_split_lock_test_and_set (operands[0], operands[1],
+2009-08-28 Uros Bizjak <ubizjak@gmail.com>
+
+ Backport from mainline:
+ 2009-08-17 Uros Bizjak <ubizjak@gmail.com>
+
+ * lib/target-supports.exp
+ (check_effective_target_vect_cmdline_needed): Add alpha to the list
+ of targets that do not need command line argument to enable SIMD.
+
2009-08-24 Richard Guenther <rguenther@suse.de>
PR middle-end/41094
verbose "check_effective_target_vect_cmdline_needed: using cached result" 2
} else {
set et_vect_cmdline_needed_saved 1
- if { [istarget ia64-*-*]
+ if { [istarget alpha*-*-*]
+ || [istarget ia64-*-*]
|| (([istarget x86_64-*-*] || [istarget i?86-*-*])
&& [check_effective_target_lp64])
|| ([istarget powerpc*-*-*]