--- /dev/null
+From ac0e0209b685878262b8b726059f328c36f46a4a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 7 Jun 2023 16:24:08 +0800
+Subject: Revert "drm/amd/display: Move DCN314 DOMAIN power control to DMCUB"
+
+From: Daniel Miess <daniel.miess@amd.com>
+
+[ Upstream commit bf0097c5c9aec528da75e2b5fcede472165322bb ]
+
+This reverts commit e383b12709e32d6494c948422070c2464b637e44.
+
+Controling hubp power gating using the DMCUB isn't stable so we
+are reverting this change to move control back into the driver.
+
+Cc: stable@vger.kernel.org # 6.3+
+Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
+Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
+Signed-off-by: Daniel Miess <daniel.miess@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../drm/amd/display/dc/dcn314/dcn314_hwseq.c | 23 -------------------
+ .../drm/amd/display/dc/dcn314/dcn314_hwseq.h | 2 --
+ .../drm/amd/display/dc/dcn314/dcn314_init.c | 2 +-
+ 3 files changed, 1 insertion(+), 26 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
+index cc3fe9cac5b53..c309933112e5e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c
+@@ -400,29 +400,6 @@ void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst,
+ hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on);
+ }
+
+-void dcn314_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on)
+-{
+- struct dc_context *ctx = hws->ctx;
+- union dmub_rb_cmd cmd;
+-
+- if (hws->ctx->dc->debug.disable_hubp_power_gate)
+- return;
+-
+- PERF_TRACE();
+-
+- memset(&cmd, 0, sizeof(cmd));
+- cmd.domain_control.header.type = DMUB_CMD__VBIOS;
+- cmd.domain_control.header.sub_type = DMUB_CMD__VBIOS_DOMAIN_CONTROL;
+- cmd.domain_control.header.payload_bytes = sizeof(cmd.domain_control.data);
+- cmd.domain_control.data.inst = hubp_inst;
+- cmd.domain_control.data.power_gate = !power_on;
+-
+- dc_dmub_srv_cmd_queue(ctx->dmub_srv, &cmd);
+- dc_dmub_srv_cmd_execute(ctx->dmub_srv);
+- dc_dmub_srv_wait_idle(ctx->dmub_srv);
+-
+- PERF_TRACE();
+-}
+ static void apply_symclk_on_tx_off_wa(struct dc_link *link)
+ {
+ /* There are use cases where SYMCLK is referenced by OTG. For instance
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
+index 6d0b62503caa6..54b1379914ce5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.h
+@@ -41,8 +41,6 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsig
+
+ void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);
+
+-void dcn314_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
+-
+ void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);
+
+ void dcn314_disable_link_output(struct dc_link *link, const struct link_resource *link_res, enum signal_type signal);
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
+index a588f46b166f4..d9d2576f3e842 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c
+@@ -138,7 +138,7 @@ static const struct hwseq_private_funcs dcn314_private_funcs = {
+ .plane_atomic_power_down = dcn10_plane_atomic_power_down,
+ .enable_power_gating_plane = dcn314_enable_power_gating_plane,
+ .dpp_root_clock_control = dcn314_dpp_root_clock_control,
+- .hubp_pg_control = dcn314_hubp_pg_control,
++ .hubp_pg_control = dcn31_hubp_pg_control,
+ .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
+ .update_odm = dcn314_update_odm,
+ .dsc_pg_control = dcn314_dsc_pg_control,
+--
+2.39.2
+