drm/amd/display: Skip to enable dsc if it has been off

commit 4bdc5b504af7de1f649004cfdd37445d36db6703 upstream.

[WHY]
It makes DSC enable when we commit the stream which need
keep power off, and then it will skip to disable DSC if
pipe reset at this situation as power has been off. It may
cause the DSC unexpected enable on the pipe with the
next new stream which doesn't support DSC.

[HOW]
Check the DSC used on current pipe status when update stream.
Skip to enable if it has been off. The operation enable
DSC should happen when set power on.

Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Zhikai Zhai <zhikai.zhai@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index f4eb28206bcb24e21de02e9dbaa51247b3dd9283..df80072174b79d8b6769536c1141300e1c9d7b29 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -1029,6 +1029,20 @@ void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
                struct dsc_config dsc_cfg;
                struct dsc_optc_config dsc_optc_cfg = {0};
                enum optc_dsc_mode optc_dsc_mode;
+               struct dcn_dsc_state dsc_state = {0};
+
+               if (!dsc) {
+                       DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);
+                       return;
+               }
+
+               if (dsc->funcs->dsc_read_state) {
+                       dsc->funcs->dsc_read_state(dsc, &dsc_state);
+                       if (!dsc_state.dsc_fw_en) {
+                               DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);
+                               return;
+                       }
+               }
 
                /* Enable DSC hw block */
                dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index d5e9aec52a059750ea3da2370028e1cbdd53987c..80db40787e019768e7ce672f7989644dd03cfc8b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -375,7 +375,20 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
                struct dsc_config dsc_cfg;
                struct dsc_optc_config dsc_optc_cfg = {0};
                enum optc_dsc_mode optc_dsc_mode;
+               struct dcn_dsc_state dsc_state = {0};
 
+               if (!dsc) {
+                       DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst);
+                       return;
+               }
+
+               if (dsc->funcs->dsc_read_state) {
+                       dsc->funcs->dsc_read_state(dsc, &dsc_state);
+                       if (!dsc_state.dsc_fw_en) {
+                               DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst);
+                               return;
+                       }
+               }
                /* Enable DSC hw block */
                dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
                dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;