drm/msm/dpu: program correct register for UBWC config on DPU 8.x+

Since DPU 8.0 there is a separate register for the second rectangle,
which needs to be programmed with the UBWC config if multirect is being
used. Write pipe's UBWC configuration to the correct register.

Fixes: 100d7ef6995d ("drm/msm/dpu: add support for SM8450")
Tested-by: Val Packett <val@packett.cool> # x1e80100-dell-latitude-7455
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/699277/
Link: https://lore.kernel.org/r/20260119-msm-ubwc-fixes-v4-3-0987acc0427f@oss.qualcomm.com

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index b66c4cb5760c9ae54e2b4667304975b5d9dfe503..6ff4902fce08ee9e11c19143f41610adb07fb27b 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -72,6 +72,8 @@
 #define SSPP_EXCL_REC_XY_REC1              0x188
 #define SSPP_EXCL_REC_SIZE                 0x1B4
 #define SSPP_EXCL_REC_XY                   0x1B8
+#define SSPP_UBWC_STATIC_CTRL_REC1         0x1c0
+#define SSPP_UBWC_ERROR_STATUS_REC1        0x1c8
 #define SSPP_CLK_CTRL                      0x330
 
 /* SSPP_SRC_OP_MODE & OP_MODE_REC1 */
@@ -215,7 +217,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
        u32 chroma_samp, unpack, src_format;
        u32 opmode = 0;
        u32 fast_clear = 0;
-       u32 op_mode_off, unpack_pat_off, format_off;
+       u32 op_mode_off, unpack_pat_off, format_off, ubwc_ctrl_off, ubwc_error_off;
 
        if (!ctx || !fmt)
                return;
@@ -225,10 +227,21 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
                op_mode_off = SSPP_SRC_OP_MODE;
                unpack_pat_off = SSPP_SRC_UNPACK_PATTERN;
                format_off = SSPP_SRC_FORMAT;
+               ubwc_ctrl_off = SSPP_UBWC_STATIC_CTRL;
+               ubwc_error_off = SSPP_UBWC_ERROR_STATUS;
        } else {
                op_mode_off = SSPP_SRC_OP_MODE_REC1;
                unpack_pat_off = SSPP_SRC_UNPACK_PATTERN_REC1;
                format_off = SSPP_SRC_FORMAT_REC1;
+
+               /* reg wasn't present before DPU 8.0 */
+               if (ctx->mdss_ver->core_major_ver >= 8) {
+                       ubwc_ctrl_off = SSPP_UBWC_STATIC_CTRL_REC1;
+                       ubwc_error_off = SSPP_UBWC_ERROR_STATUS_REC1;
+               } else {
+                       ubwc_ctrl_off = SSPP_UBWC_STATIC_CTRL;
+                       ubwc_error_off = SSPP_UBWC_ERROR_STATUS;
+               }
        }
 
        c = &ctx->hw;
@@ -281,24 +294,24 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
                switch (ctx->ubwc->ubwc_enc_version) {
                case UBWC_1_0:
                        fast_clear = fmt->alpha_enable ? BIT(31) : 0;
-                       DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
+                       DPU_REG_WRITE(c, ubwc_ctrl_off,
                                        fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) |
                                        BIT(8) |
                                        (hbb << 4));
                        break;
                case UBWC_2_0:
                        fast_clear = fmt->alpha_enable ? BIT(31) : 0;
-                       DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
+                       DPU_REG_WRITE(c, ubwc_ctrl_off,
                                        fast_clear | (ctx->ubwc->ubwc_swizzle) |
                                        (hbb << 4));
                        break;
                case UBWC_3_0:
-                       DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
+                       DPU_REG_WRITE(c, ubwc_ctrl_off,
                                        BIT(30) | (ctx->ubwc->ubwc_swizzle) |
                                        (hbb << 4));
                        break;
                case UBWC_4_0:
-                       DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
+                       DPU_REG_WRITE(c, ubwc_ctrl_off,
                                        MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
                        break;
                }
@@ -327,7 +340,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
        DPU_REG_WRITE(c, op_mode_off, opmode);
 
        /* clear previous UBWC error */
-       DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS, BIT(31));
+       DPU_REG_WRITE(c, ubwc_error_off, BIT(31));
 }
 
 static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,