drm/i915/cx0: Sanitize C10 PHY PLL SSC register setup

Define the C10 PLL SSC register range via macros, so the HW/SW state of
these register can be verified by a follow-up change, reusing these
macros.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20251117104602.2363671-10-mika.kahola@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 2ab93d02fdf189be93bc5192b0ccc859396eaa22..f190762e4871e7e7daafc7f2cf6b619bb9728b80 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2059,6 +2059,9 @@ static void intel_cx0pll_update_ssc(struct intel_encoder *encoder,
        }
 }
 
+#define C10_PLL_SSC_REG_START_IDX      4
+#define C10_PLL_SSC_REG_COUNT          5
+
 static void intel_c10pll_update_pll(struct intel_encoder *encoder,
                                    struct intel_cx0pll_state *pll_state)
 {
@@ -2068,8 +2071,11 @@ static void intel_c10pll_update_pll(struct intel_encoder *encoder,
        if (pll_state->ssc_enabled)
                return;
 
-       drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) < 9);
-       for (i = 4; i < 9; i++)
+       drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) <
+                                 C10_PLL_SSC_REG_START_IDX + C10_PLL_SSC_REG_COUNT);
+       for (i = C10_PLL_SSC_REG_START_IDX;
+            i < C10_PLL_SSC_REG_START_IDX + C10_PLL_SSC_REG_COUNT;
+            i++)
                pll_state->c10.pll[i] = 0;
 }