RISC-V: Add missed cond autovec testcases

This patch adds all missed cond autovec testcases. For not support
cond patterns, the following patches will be sent to fix it.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c: Add vrem op.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c: Ditto.
	* gcc.target/riscv/rvv/autovec/cond/cond_logical_run-1.c: Moved to...
	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c: ...here.
	* gcc.target/riscv/rvv/autovec/cond/cond_logical_run-2.c: Moved to...
	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c: ...here.
	* gcc.target/riscv/rvv/autovec/cond/cond_logical_run-3.c: Moved to...
	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c: ...here.
	* gcc.target/riscv/rvv/autovec/cond/cond_logical_run-4.c: Moved to...
	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c: ...here.
	* gcc.target/riscv/rvv/autovec/cond/cond_logical_run-5.c: Moved to...
	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c: ...here.
	* gcc.target/riscv/rvv/autovec/cond/cond_logical-1.c: Removed.
	* gcc.target/riscv/rvv/autovec/cond/cond_logical-2.c: Removed.
	* gcc.target/riscv/rvv/autovec/cond/cond_logical-3.c: Removed.
	* gcc.target/riscv/rvv/autovec/cond/cond_logical-4.c: Removed.
	* gcc.target/riscv/rvv/autovec/cond/cond_logical-5.c: Removed.
	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c: New test.
	* gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c: New test.

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c
index e05226cb2e0f36de1aca49f909ebd108774d55f2..922be4d7d349a64e23d7b82983551e5850f795b0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-1.c
@@ -18,6 +18,8 @@
   TEST (TYPE, mul, *)                                                          \
   TEST (TYPE, div, /)
 
+#define TEST_TYPE2(TYPE) TEST (TYPE, rem, %)
+
 #define TEST_ALL                                                               \
   TEST_TYPE (int8_t)                                                           \
   TEST_TYPE (uint8_t)                                                          \
@@ -27,6 +29,14 @@
   TEST_TYPE (uint32_t)                                                         \
   TEST_TYPE (int64_t)                                                          \
   TEST_TYPE (uint64_t)                                                         \
+  TEST_TYPE2 (int8_t)                                                          \
+  TEST_TYPE2 (uint8_t)                                                         \
+  TEST_TYPE2 (int16_t)                                                         \
+  TEST_TYPE2 (uint16_t)                                                        \
+  TEST_TYPE2 (int32_t)                                                         \
+  TEST_TYPE2 (uint32_t)                                                        \
+  TEST_TYPE2 (int64_t)                                                         \
+  TEST_TYPE2 (uint64_t)                                                        \
   TEST_TYPE (_Float16)                                                         \
   TEST_TYPE (float)                                                            \
   TEST_TYPE (double)
@@ -34,6 +44,7 @@
 TEST_ALL
 
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 8 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_MOD" 8 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_ADD" 11 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_SUB" 11 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_MUL" 11 "optimized" } } */
@@ -42,6 +53,8 @@ TEST_ALL
 /* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
 /* { dg-final { scan-assembler-times {vmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
 /* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
 /* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
 /* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
 /* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c
index 2b73536b13a588d863e6be41920d8b1aeb45f9fe..986a70e45077e427d4cee2000183385a41c061d5 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-2.c
@@ -4,6 +4,7 @@
 #include "cond_arith-1.c"
 
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 8 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_MOD" 8 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_RDIV" 3 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_ADD" 8 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_SUB" 8 "optimized" } } */
@@ -21,6 +22,8 @@
 /* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
 /* { dg-final { scan-assembler-times {vmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
 /* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
 /* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
 /* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
 /* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c
index 5fdeb3837ea00b9d2ac3ff09cdc0d5dfd36efb95..a97d34facd8a6dcbd9a8100c1051f50ed0e24407 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-3.c
@@ -20,6 +20,8 @@
   TEST (DATA_TYPE, PRED_TYPE, mul, *)                                          \
   TEST (DATA_TYPE, PRED_TYPE, div, /)
 
+#define TEST_TYPE2(DATA_TYPE, PRED_TYPE) TEST (DATA_TYPE, PRED_TYPE, rem, %)
+
 #define TEST_ALL                                                               \
   TEST_TYPE (int32_t, int8_t)                                                  \
   TEST_TYPE (uint32_t, int8_t)                                                 \
@@ -31,6 +33,16 @@
   TEST_TYPE (uint64_t, int16_t)                                                \
   TEST_TYPE (int64_t, int32_t)                                                 \
   TEST_TYPE (uint64_t, int32_t)                                                \
+  TEST_TYPE2 (int32_t, int8_t)                                                 \
+  TEST_TYPE2 (uint32_t, int8_t)                                                \
+  TEST_TYPE2 (int32_t, int16_t)                                                \
+  TEST_TYPE2 (uint32_t, int16_t)                                               \
+  TEST_TYPE2 (int64_t, int8_t)                                                 \
+  TEST_TYPE2 (uint64_t, int8_t)                                                \
+  TEST_TYPE2 (int64_t, int16_t)                                                \
+  TEST_TYPE2 (uint64_t, int16_t)                                               \
+  TEST_TYPE2 (int64_t, int32_t)                                                \
+  TEST_TYPE2 (uint64_t, int32_t)                                               \
   TEST_TYPE (_Float16, int8_t)                                                 \
   TEST_TYPE (float, int8_t)                                                    \
   TEST_TYPE (float, int16_t)                                                   \
@@ -41,6 +53,7 @@
 TEST_ALL
 
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 10 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_MOD" 10 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_ADD" 16 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_SUB" 16 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_MUL" 16 "optimized" } } */
@@ -49,6 +62,8 @@ TEST_ALL
 /* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 10 } } */
 /* { dg-final { scan-assembler-times {vmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 10 } } */
 /* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 10 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 5 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 5 } } */
 /* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
 /* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
 /* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c
index 0cbe9bbb479a00a76a405fac3870c7f4d64ba416..30089b784b970ec2fda4a2a3f7e7d3bcdd775dd8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-4.c
@@ -4,6 +4,7 @@
 #include "cond_arith-3.c"
 
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 10 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_MOD" 10 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_ADD" 10 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_SUB" 10 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_MUL" 10 "optimized" } } */
@@ -15,6 +16,8 @@
 /* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 10 } } */
 /* { dg-final { scan-assembler-times {vmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 10 } } */
 /* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 10 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 5 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 5 } } */
 /* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
 /* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
 /* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c
index cf9c95066c382275d2cff8aa549e33fb0f4bbefa..2f9e883ff25f10f6972083a87585d3bda7b306d1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-5.c
@@ -18,6 +18,8 @@
   TEST (TYPE, mul, *)                                                          \
   TEST (TYPE, div, /)
 
+#define TEST_TYPE2(TYPE) TEST (TYPE, rem, %)
+
 #define TEST_ALL                                                               \
   TEST_TYPE (int8_t)                                                           \
   TEST_TYPE (uint8_t)                                                          \
@@ -27,6 +29,14 @@
   TEST_TYPE (uint32_t)                                                         \
   TEST_TYPE (int64_t)                                                          \
   TEST_TYPE (uint64_t)                                                         \
+  TEST_TYPE2 (int8_t)                                                           \
+  TEST_TYPE2 (uint8_t)                                                          \
+  TEST_TYPE2 (int16_t)                                                          \
+  TEST_TYPE2 (uint16_t)                                                         \
+  TEST_TYPE2 (int32_t)                                                          \
+  TEST_TYPE2 (uint32_t)                                                         \
+  TEST_TYPE2 (int64_t)                                                          \
+  TEST_TYPE2 (uint64_t)                                                         \
   TEST_TYPE (_Float16)                                                         \
   TEST_TYPE (float)                                                            \
   TEST_TYPE (double)
@@ -34,6 +44,7 @@
 TEST_ALL
 
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 8 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_MOD" 8 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_ADD" 11 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_SUB" 11 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_MUL" 11 "optimized" } } */
@@ -42,6 +53,8 @@ TEST_ALL
 /* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
 /* { dg-final { scan-assembler-times {vmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
 /* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
 /* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
 /* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
 /* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c
index 487cf51a41109eb2c14402f1a4858582b2941388..13a230cca4f1061c25e3b26531a44fce32ae7d94 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-6.c
@@ -4,6 +4,7 @@
 #include "cond_arith-5.c"
 
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 8 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_MOD" 8 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_RDIV" 3 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_ADD" 8 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_SUB" 8 "optimized" } } */
@@ -21,6 +22,8 @@
 /* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
 /* { dg-final { scan-assembler-times {vmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
 /* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
 /* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
 /* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
 /* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c
index 8d4fa880710769256f1ce58c8a9ae2b681049a30..e43f040cd1a8c7d8dcc13fe86603b23c5c8c7bab 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-7.c
@@ -21,11 +21,17 @@
   TEST (TYPE, mul, *)                                                          \
   TEST (TYPE, div, /)
 
+#define TEST_TYPE2(TYPE) TEST (TYPE, rem, %)
+
 #define TEST_ALL                                                               \
   TEST_TYPE (int32_t)                                                          \
   TEST_TYPE (uint32_t)                                                         \
   TEST_TYPE (int64_t)                                                          \
   TEST_TYPE (uint64_t)                                                         \
+  TEST_TYPE2 (int32_t)                                                         \
+  TEST_TYPE2 (uint32_t)                                                        \
+  TEST_TYPE2 (int64_t)                                                         \
+  TEST_TYPE2 (uint64_t)                                                        \
   TEST_TYPE (_Float16)                                                         \
   TEST_TYPE (float)                                                            \
   TEST_TYPE (double)
@@ -33,6 +39,7 @@
 TEST_ALL
 
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 4 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_MOD" 4 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_RDIV" 3 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_ADD" 4 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 3 "optimized" } } */
@@ -44,6 +51,8 @@ TEST_ALL
 /* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
 /* { dg-final { scan-assembler-times {vmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
 /* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */
 /* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
 /* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
 /* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c
index d191d4cebab5eae2a655e65df17f76cff06c54b9..eac77e08b75d2517545f11e675142e2a7a2842af 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-8.c
@@ -26,6 +26,8 @@
   TEST (DATA_TYPE, OTHER_TYPE, mul, *)                                         \
   TEST (DATA_TYPE, OTHER_TYPE, div, /)
 
+#define TEST_TYPE2(DATA_TYPE, OTHER_TYPE) TEST (DATA_TYPE, OTHER_TYPE, rem, %)
+
 #define TEST_ALL                                                               \
   TEST_TYPE (int32_t, int8_t)                                                  \
   TEST_TYPE (int32_t, int16_t)                                                 \
@@ -37,6 +39,16 @@
   TEST_TYPE (uint64_t, int8_t)                                                 \
   TEST_TYPE (uint64_t, int16_t)                                                \
   TEST_TYPE (uint64_t, int32_t)                                                \
+  TEST_TYPE2 (int32_t, int8_t)                                                 \
+  TEST_TYPE2 (int32_t, int16_t)                                                \
+  TEST_TYPE2 (uint32_t, int8_t)                                                \
+  TEST_TYPE2 (uint32_t, int16_t)                                               \
+  TEST_TYPE2 (int64_t, int8_t)                                                 \
+  TEST_TYPE2 (int64_t, int16_t)                                                \
+  TEST_TYPE2 (int64_t, int32_t)                                                \
+  TEST_TYPE2 (uint64_t, int8_t)                                                \
+  TEST_TYPE2 (uint64_t, int16_t)                                               \
+  TEST_TYPE2 (uint64_t, int32_t)                                               \
   TEST_TYPE (_Float16, int8_t)                                                 \
   TEST_TYPE (float, int8_t)                                                    \
   TEST_TYPE (float, int16_t)                                                   \
@@ -53,11 +65,14 @@ TEST_ALL
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_SUB" 22 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_MUL" 22 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 40 "optimized" } } */
+/* { dg-final { scan-tree-dump-times "\.COND_LEN_MOD" 40 "optimized" } } */
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_RDIV" 22 "optimized" } } */
-/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+} 104 } } */
+/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+} 114 } } */
 /* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 40 } } */
 /* { dg-final { scan-assembler-times {vmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 40 } } */
 /* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 40 } } */
+/* { dg-final { scan-assembler-times {vrem\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 20 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 20 } } */
 /* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 22 } } */
 /* { dg-final { scan-assembler-times {vfsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 22 } } */
 /* { dg-final { scan-assembler-times {vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 22 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c
index 38bb613c67eb39828a79bcbae66c2b812420384d..fc8b3512e92773b38a04a808a56f546fce7d5ed9 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_arith-9.c
@@ -18,6 +18,8 @@
   TEST (TYPE, mul, *)                                                          \
   TEST (TYPE, div, /)
 
+#define TEST_TYPE2(TYPE) TEST (TYPE, rem, %)
+
 #define TEST_ALL                                                               \
   TEST_TYPE (int8_t)                                                           \
   TEST_TYPE (uint8_t)                                                          \
@@ -26,7 +28,14 @@
   TEST_TYPE (int32_t)                                                          \
   TEST_TYPE (uint32_t)                                                         \
   TEST_TYPE (int64_t)                                                          \
-  TEST_TYPE (uint64_t)                                                         \
+  TEST_TYPE2 (int8_t)                                                          \
+  TEST_TYPE2 (uint8_t)                                                         \
+  TEST_TYPE2 (int16_t)                                                         \
+  TEST_TYPE2 (uint16_t)                                                        \
+  TEST_TYPE2 (int32_t)                                                         \
+  TEST_TYPE2 (uint32_t)                                                        \
+  TEST_TYPE2 (int64_t)                                                         \
+  TEST_TYPE2 (uint64_t)                                                        \
   TEST_TYPE (_Float16)                                                         \
   TEST_TYPE (float)                                                            \
   TEST_TYPE (double)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-1.c
deleted file mode 100644 (file)
index af1a261..0000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-1.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
-
-#include <stdint-gcc.h>
-
-#define bit_and(A, B) ((A) & (B))
-#define bit_or(A, B) ((A) | (B))
-#define bit_xor(A, B) ((A) ^ (B))
-#define bit_bic(A, B) ((A) & ~(B))
-
-#define DEF_LOOP(TYPE, OP)                             \
-  void __attribute__ ((noinline, noclone))             \
-  test_##TYPE##_##OP (TYPE *__restrict r,              \
-                     TYPE *__restrict a,               \
-                     TYPE *__restrict b,               \
-                     TYPE *__restrict c, int n)        \
-  {                                                    \
-    for (int i = 0; i < n; ++i)                                \
-      r[i] = a[i] < 20 ? OP (b[i], c[i]) : b[i];       \
-  }
-
-#define TEST_TYPE(T, TYPE) \
-  T (TYPE, bit_and) \
-  T (TYPE, bit_or) \
-  T (TYPE, bit_xor) \
-  T (TYPE, bit_bic)
-
-#define TEST_ALL(T) \
-  TEST_TYPE (T, int8_t) \
-  TEST_TYPE (T, uint8_t) \
-  TEST_TYPE (T, int16_t) \
-  TEST_TYPE (T, uint16_t) \
-  TEST_TYPE (T, int32_t) \
-  TEST_TYPE (T, uint32_t) \
-  TEST_TYPE (T, int64_t) \
-  TEST_TYPE (T, uint64_t)
-
-TEST_ALL (DEF_LOOP)
-
-/* { dg-final { scan-assembler-times {vnot\.v\s+v[0-9]+,v[0-9]+} 8 } } */
-/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 16 } } */
-/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
-/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-2.c
deleted file mode 100644 (file)
index 5f7614d..0000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-2.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
-
-#include <stdint-gcc.h>
-
-#define bit_and(A, B) ((A) & (B))
-#define bit_or(A, B) ((A) | (B))
-#define bit_xor(A, B) ((A) ^ (B))
-#define bit_bic(A, B) ((A) & ~(B))
-
-#define DEF_LOOP(TYPE, OP)                             \
-  void __attribute__ ((noinline, noclone))             \
-  test_##TYPE##_##OP (TYPE *__restrict r,              \
-                     TYPE *__restrict a,               \
-                     TYPE *__restrict b,               \
-                     TYPE *__restrict c, int n)        \
-  {                                                    \
-    for (int i = 0; i < n; ++i)                                \
-      r[i] = a[i] < 20 ? OP (b[i], c[i]) : c[i];       \
-  }
-
-#define TEST_TYPE(T, TYPE) \
-  T (TYPE, bit_and) \
-  T (TYPE, bit_or) \
-  T (TYPE, bit_xor) \
-  T (TYPE, bit_bic)
-
-#define TEST_ALL(T) \
-  TEST_TYPE (T, int8_t) \
-  TEST_TYPE (T, uint8_t) \
-  TEST_TYPE (T, int16_t) \
-  TEST_TYPE (T, uint16_t) \
-  TEST_TYPE (T, int32_t) \
-  TEST_TYPE (T, uint32_t) \
-  TEST_TYPE (T, int64_t) \
-  TEST_TYPE (T, uint64_t)
-
-TEST_ALL (DEF_LOOP)
-
-/* { dg-final { scan-assembler-times {vnot\.v\s+v[0-9]+,v[0-9]+} 8 } } */
-/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 16 } } */
-/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
-/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-3.c
deleted file mode 100644 (file)
index 032d12c..0000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-3.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
-
-#include <stdint-gcc.h>
-
-#define bit_and(A, B) ((A) & (B))
-#define bit_or(A, B) ((A) | (B))
-#define bit_xor(A, B) ((A) ^ (B))
-#define bit_bic(A, B) ((A) & ~(B))
-
-#define DEF_LOOP(TYPE, OP)                             \
-  void __attribute__ ((noinline, noclone))             \
-  test_##TYPE##_##OP (TYPE *__restrict r,              \
-                     TYPE *__restrict a,               \
-                     TYPE *__restrict b,               \
-                     TYPE *__restrict c, int n)        \
-  {                                                    \
-    for (int i = 0; i < n; ++i)                                \
-      r[i] = a[i] < 20 ? OP (b[i], c[i]) : a[i];       \
-  }
-
-#define TEST_TYPE(T, TYPE) \
-  T (TYPE, bit_and) \
-  T (TYPE, bit_or) \
-  T (TYPE, bit_xor) \
-  T (TYPE, bit_bic)
-
-#define TEST_ALL(T) \
-  TEST_TYPE (T, int8_t) \
-  TEST_TYPE (T, uint8_t) \
-  TEST_TYPE (T, int16_t) \
-  TEST_TYPE (T, uint16_t) \
-  TEST_TYPE (T, int32_t) \
-  TEST_TYPE (T, uint32_t) \
-  TEST_TYPE (T, int64_t) \
-  TEST_TYPE (T, uint64_t)
-
-TEST_ALL (DEF_LOOP)
-
-/* { dg-final { scan-assembler-times {vnot\.v\s+v[0-9]+,v[0-9]+} 8 } } */
-/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 16 } } */
-/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
-/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-4.c
deleted file mode 100644 (file)
index e8d9337..0000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-4.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
-
-#include <stdint-gcc.h>
-
-#define bit_and(A, B) ((A) & (B))
-#define bit_or(A, B) ((A) | (B))
-#define bit_xor(A, B) ((A) ^ (B))
-#define bit_bic(A, B) ((A) & ~(B))
-
-#define DEF_LOOP(TYPE, OP)                             \
-  void __attribute__ ((noinline, noclone))             \
-  test_##TYPE##_##OP (TYPE *__restrict r,              \
-                     TYPE *__restrict a,               \
-                     TYPE *__restrict b,               \
-                     TYPE *__restrict c, int n)        \
-  {                                                    \
-    for (int i = 0; i < n; ++i)                                \
-      r[i] = a[i] < 20 ? OP (b[i], c[i]) : 42;         \
-  }
-
-#define TEST_TYPE(T, TYPE) \
-  T (TYPE, bit_and) \
-  T (TYPE, bit_or) \
-  T (TYPE, bit_xor) \
-  T (TYPE, bit_bic)
-
-#define TEST_ALL(T) \
-  TEST_TYPE (T, int8_t) \
-  TEST_TYPE (T, uint8_t) \
-  TEST_TYPE (T, int16_t) \
-  TEST_TYPE (T, uint16_t) \
-  TEST_TYPE (T, int32_t) \
-  TEST_TYPE (T, uint32_t) \
-  TEST_TYPE (T, int64_t) \
-  TEST_TYPE (T, uint64_t)
-
-TEST_ALL (DEF_LOOP)
-
-/* { dg-final { scan-assembler-times {vnot\.v\s+v[0-9]+,v[0-9]+} 8 } } */
-/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 16 } } */
-/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
-/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-5.c
deleted file mode 100644 (file)
index c59ef51..0000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical-5.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* { dg-do compile } */
-/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
-
-#include <stdint-gcc.h>
-
-#define bit_and(A, B) ((A) & (B))
-#define bit_or(A, B) ((A) | (B))
-#define bit_xor(A, B) ((A) ^ (B))
-#define bit_bic(A, B) ((A) & ~(B))
-
-#define DEF_LOOP(TYPE, OP)                             \
-  void __attribute__ ((noinline, noclone))             \
-  test_##TYPE##_##OP (TYPE *__restrict r,              \
-                     TYPE *__restrict a,               \
-                     TYPE *__restrict b,               \
-                     TYPE *__restrict c, int n)        \
-  {                                                    \
-    for (int i = 0; i < n; ++i)                                \
-      r[i] = a[i] < 20 ? OP (b[i], c[i]) : 0;          \
-  }
-
-#define TEST_TYPE(T, TYPE) \
-  T (TYPE, bit_and) \
-  T (TYPE, bit_or) \
-  T (TYPE, bit_xor) \
-  T (TYPE, bit_bic)
-
-#define TEST_ALL(T) \
-  TEST_TYPE (T, int8_t) \
-  TEST_TYPE (T, uint8_t) \
-  TEST_TYPE (T, int16_t) \
-  TEST_TYPE (T, uint16_t) \
-  TEST_TYPE (T, int32_t) \
-  TEST_TYPE (T, uint32_t) \
-  TEST_TYPE (T, int64_t) \
-  TEST_TYPE (T, uint64_t)
-
-TEST_ALL (DEF_LOOP)
-
-/* { dg-final { scan-assembler-times {vnot\.v\s+v[0-9]+,v[0-9]+} 8 } } */
-/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 16 } } */
-/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
-/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c
new file mode 100644 (file)
index 0000000..7034786
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-1.c
@@ -0,0 +1,49 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include <stdint-gcc.h>
+
+#define bit_and(A, B) ((A) & (B))
+#define bit_or(A, B) ((A) | (B))
+#define bit_xor(A, B) ((A) ^ (B))
+#define bit_bic(A, B) ((A) & ~(B))
+#define min(A, B) ((A) <= (B) ? (A) : (B))
+#define max(A, B) ((A) >= (B) ? (A) : (B))
+
+#define DEF_LOOP(TYPE, OP)                                                     \
+  void __attribute__ ((noinline, noclone))                                     \
+  test_##TYPE##_##OP (TYPE *__restrict r, TYPE *__restrict a,                  \
+                     TYPE *__restrict b, TYPE *__restrict c, int n)           \
+  {                                                                            \
+    for (int i = 0; i < n; ++i)                                                \
+      r[i] = a[i] < 20 ? OP (b[i], c[i]) : b[i];                               \
+  }
+
+#define TEST_TYPE(T, TYPE)                                                     \
+  T (TYPE, bit_and)                                                            \
+  T (TYPE, bit_or)                                                             \
+  T (TYPE, bit_xor)                                                            \
+  T (TYPE, bit_bic)                                                            \
+  T (TYPE, min)                                                                \
+  T (TYPE, max)
+
+#define TEST_ALL(T)                                                            \
+  TEST_TYPE (T, int8_t)                                                        \
+  TEST_TYPE (T, uint8_t)                                                       \
+  TEST_TYPE (T, int16_t)                                                       \
+  TEST_TYPE (T, uint16_t)                                                      \
+  TEST_TYPE (T, int32_t)                                                       \
+  TEST_TYPE (T, uint32_t)                                                      \
+  TEST_TYPE (T, int64_t)                                                       \
+  TEST_TYPE (T, uint64_t)
+
+TEST_ALL (DEF_LOOP)
+
+/* { dg-final { scan-assembler-times {vnot\.v\s+v[0-9]+,v[0-9]+} 8 } } */
+/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 16 } } */
+/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
+/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
+/* { dg-final { scan-assembler-times {vmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times {vminu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times {vmaxu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c
new file mode 100644 (file)
index 0000000..44cbbe6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-2.c
@@ -0,0 +1,49 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include <stdint-gcc.h>
+
+#define bit_and(A, B) ((A) & (B))
+#define bit_or(A, B) ((A) | (B))
+#define bit_xor(A, B) ((A) ^ (B))
+#define bit_bic(A, B) ((A) & ~(B))
+#define min(A, B) ((A) <= (B) ? (A) : (B))
+#define max(A, B) ((A) >= (B) ? (A) : (B))
+
+#define DEF_LOOP(TYPE, OP)                                                     \
+  void __attribute__ ((noinline, noclone))                                     \
+  test_##TYPE##_##OP (TYPE *__restrict r, TYPE *__restrict a,                  \
+                     TYPE *__restrict b, TYPE *__restrict c, int n)           \
+  {                                                                            \
+    for (int i = 0; i < n; ++i)                                                \
+      r[i] = a[i] < 20 ? OP (b[i], c[i]) : c[i];                               \
+  }
+
+#define TEST_TYPE(T, TYPE)                                                     \
+  T (TYPE, bit_and)                                                            \
+  T (TYPE, bit_or)                                                             \
+  T (TYPE, bit_xor)                                                            \
+  T (TYPE, bit_bic)                                                            \
+  T (TYPE, min)                                                                \
+  T (TYPE, max)
+
+#define TEST_ALL(T)                                                            \
+  TEST_TYPE (T, int8_t)                                                        \
+  TEST_TYPE (T, uint8_t)                                                       \
+  TEST_TYPE (T, int16_t)                                                       \
+  TEST_TYPE (T, uint16_t)                                                      \
+  TEST_TYPE (T, int32_t)                                                       \
+  TEST_TYPE (T, uint32_t)                                                      \
+  TEST_TYPE (T, int64_t)                                                       \
+  TEST_TYPE (T, uint64_t)
+
+TEST_ALL (DEF_LOOP)
+
+/* { dg-final { scan-assembler-times {vnot\.v\s+v[0-9]+,v[0-9]+} 8 } } */
+/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 16 } } */
+/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
+/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
+/* { dg-final { scan-assembler-times {vmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times {vminu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times {vmaxu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c
new file mode 100644 (file)
index 0000000..220a376
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-3.c
@@ -0,0 +1,49 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include <stdint-gcc.h>
+
+#define bit_and(A, B) ((A) & (B))
+#define bit_or(A, B) ((A) | (B))
+#define bit_xor(A, B) ((A) ^ (B))
+#define bit_bic(A, B) ((A) & ~(B))
+#define min(A, B) ((A) <= (B) ? (A) : (B))
+#define max(A, B) ((A) >= (B) ? (A) : (B))
+
+#define DEF_LOOP(TYPE, OP)                                                     \
+  void __attribute__ ((noinline, noclone))                                     \
+  test_##TYPE##_##OP (TYPE *__restrict r, TYPE *__restrict a,                  \
+                     TYPE *__restrict b, TYPE *__restrict c, int n)           \
+  {                                                                            \
+    for (int i = 0; i < n; ++i)                                                \
+      r[i] = a[i] < 20 ? OP (b[i], c[i]) : a[i];                               \
+  }
+
+#define TEST_TYPE(T, TYPE)                                                     \
+  T (TYPE, bit_and)                                                            \
+  T (TYPE, bit_or)                                                             \
+  T (TYPE, bit_xor)                                                            \
+  T (TYPE, bit_bic)                                                            \
+  T (TYPE, min)                                                                \
+  T (TYPE, max)
+
+#define TEST_ALL(T)                                                            \
+  TEST_TYPE (T, int8_t)                                                        \
+  TEST_TYPE (T, uint8_t)                                                       \
+  TEST_TYPE (T, int16_t)                                                       \
+  TEST_TYPE (T, uint16_t)                                                      \
+  TEST_TYPE (T, int32_t)                                                       \
+  TEST_TYPE (T, uint32_t)                                                      \
+  TEST_TYPE (T, int64_t)                                                       \
+  TEST_TYPE (T, uint64_t)
+
+TEST_ALL (DEF_LOOP)
+
+/* { dg-final { scan-assembler-times {vnot\.v\s+v[0-9]+,v[0-9]+} 8 } } */
+/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 16 } } */
+/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
+/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
+/* { dg-final { scan-assembler-times {vmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times {vminu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times {vmaxu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c
new file mode 100644 (file)
index 0000000..0763d92
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-4.c
@@ -0,0 +1,49 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include <stdint-gcc.h>
+
+#define bit_and(A, B) ((A) & (B))
+#define bit_or(A, B) ((A) | (B))
+#define bit_xor(A, B) ((A) ^ (B))
+#define bit_bic(A, B) ((A) & ~(B))
+#define min(A, B) ((A) <= (B) ? (A) : (B))
+#define max(A, B) ((A) >= (B) ? (A) : (B))
+
+#define DEF_LOOP(TYPE, OP)                                                     \
+  void __attribute__ ((noinline, noclone))                                     \
+  test_##TYPE##_##OP (TYPE *__restrict r, TYPE *__restrict a,                  \
+                     TYPE *__restrict b, TYPE *__restrict c, int n)           \
+  {                                                                            \
+    for (int i = 0; i < n; ++i)                                                \
+      r[i] = a[i] < 20 ? OP (b[i], c[i]) : 42;                                 \
+  }
+
+#define TEST_TYPE(T, TYPE)                                                     \
+  T (TYPE, bit_and)                                                            \
+  T (TYPE, bit_or)                                                             \
+  T (TYPE, bit_xor)                                                            \
+  T (TYPE, bit_bic)                                                            \
+  T (TYPE, min)                                                                \
+  T (TYPE, max)
+
+#define TEST_ALL(T)                                                            \
+  TEST_TYPE (T, int8_t)                                                        \
+  TEST_TYPE (T, uint8_t)                                                       \
+  TEST_TYPE (T, int16_t)                                                       \
+  TEST_TYPE (T, uint16_t)                                                      \
+  TEST_TYPE (T, int32_t)                                                       \
+  TEST_TYPE (T, uint32_t)                                                      \
+  TEST_TYPE (T, int64_t)                                                       \
+  TEST_TYPE (T, uint64_t)
+
+TEST_ALL (DEF_LOOP)
+
+/* { dg-final { scan-assembler-times {vnot\.v\s+v[0-9]+,v[0-9]+} 8 } } */
+/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 16 } } */
+/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
+/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
+/* { dg-final { scan-assembler-times {vmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times {vminu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times {vmaxu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c
new file mode 100644 (file)
index 0000000..304c9ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max-5.c
@@ -0,0 +1,49 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
+
+#include <stdint-gcc.h>
+
+#define bit_and(A, B) ((A) & (B))
+#define bit_or(A, B) ((A) | (B))
+#define bit_xor(A, B) ((A) ^ (B))
+#define bit_bic(A, B) ((A) & ~(B))
+#define min(A, B) ((A) <= (B) ? (A) : (B))
+#define max(A, B) ((A) >= (B) ? (A) : (B))
+
+#define DEF_LOOP(TYPE, OP)                                                     \
+  void __attribute__ ((noinline, noclone))                                     \
+  test_##TYPE##_##OP (TYPE *__restrict r, TYPE *__restrict a,                  \
+                     TYPE *__restrict b, TYPE *__restrict c, int n)           \
+  {                                                                            \
+    for (int i = 0; i < n; ++i)                                                \
+      r[i] = a[i] < 20 ? OP (b[i], c[i]) : 0;                                  \
+  }
+
+#define TEST_TYPE(T, TYPE)                                                     \
+  T (TYPE, bit_and)                                                            \
+  T (TYPE, bit_or)                                                             \
+  T (TYPE, bit_xor)                                                            \
+  T (TYPE, bit_bic)                                                            \
+  T (TYPE, min)                                                                \
+  T (TYPE, max)
+
+#define TEST_ALL(T)                                                            \
+  TEST_TYPE (T, int8_t)                                                        \
+  TEST_TYPE (T, uint8_t)                                                       \
+  TEST_TYPE (T, int16_t)                                                       \
+  TEST_TYPE (T, uint16_t)                                                      \
+  TEST_TYPE (T, int32_t)                                                       \
+  TEST_TYPE (T, uint32_t)                                                      \
+  TEST_TYPE (T, int64_t)                                                       \
+  TEST_TYPE (T, uint64_t)
+
+TEST_ALL (DEF_LOOP)
+
+/* { dg-final { scan-assembler-times {vnot\.v\s+v[0-9]+,v[0-9]+} 8 } } */
+/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 16 } } */
+/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
+/* { dg-final { scan-assembler-times {vxor\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 8 } } */
+/* { dg-final { scan-assembler-times {vmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times {vminu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-times {vmaxu\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c
similarity index 95%
rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-1.c
rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c
index e741f7d6aaca2bd418bee31ffe2109e19d700c16..439cc90070b268886eda266aaad59117cea84cad 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-1.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_vector } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
 
-#include "cond_logical-1.c"
+#include "cond_logical_min_max-1.c"
 
 #define N 99
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c
similarity index 95%
rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-2.c
rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c
index bdd697ec991348b1352094b93afd3add964e62cb..e7cf6a8c644fac14b14d1350d2c935d75fa73dfb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-2.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_vector } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
 
-#include "cond_logical-2.c"
+#include "cond_logical_min_max-2.c"
 
 #define N 99
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c
similarity index 95%
rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-3.c
rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c
index b48bcb19d2691ae7a95f70e74814bd4b7d642fdd..60054988e70e9fe1e2deccfd15c9c486e9443e3c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-3.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_vector } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
 
-#include "cond_logical-3.c"
+#include "cond_logical_min_max-3.c"
 
 #define N 99
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c
similarity index 95%
rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-4.c
rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c
index 0d04e69177f9c55588d0f99b5fb6713439da8eaa..f8016a3d01fc7a111926d3b83dce69ebe76b4988 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-4.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_vector } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
 
-#include "cond_logical-4.c"
+#include "cond_logical_min_max-4.c"
 
 #define N 99
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c
similarity index 95%
rename from gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-5.c
rename to gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c
index 87501057c20df0d9cb3435c2553a78dd2ae53d5f..e265b6f9e6e31eb14e1344a56b4531f998da38a6 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_run-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_logical_min_max_run-5.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_vector } } } */
 /* { dg-additional-options "--param=riscv-autovec-preference=scalable -fno-vect-cost-model" } */
 
-#include "cond_logical-5.c"
+#include "cond_logical_min_max-5.c"
 
 #define N 99
 

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c
new file mode 100644 (file)
index 0000000..c67593d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE1, TYPE2)                                                \
+  __attribute__ ((noipa)) void vwadd_##TYPE1_##TYPE2 (                         \
+    TYPE1 *__restrict dst, TYPE1 *__restrict dst2, TYPE1 *__restrict dst3,     \
+    TYPE2 *__restrict a, TYPE2 *__restrict b, TYPE2 *__restrict a2,            \
+    TYPE2 *__restrict b2, int *__restrict pred, int n)                         \
+  {                                                                            \
+    for (int i = 0; i < n; i++)                                                \
+      {                                                                        \
+       dst[i] = pred[i] ? (TYPE1) a[i] + (TYPE1) b[i] : dst[i];               \
+       dst2[i] = pred[i] ? (TYPE1) a2[i] + (TYPE1) b[i] : dst[i];             \
+       dst3[i] = pred[i] ? (TYPE1) a2[i] + (TYPE1) a[i] : dst2[i];            \
+      }                                                                        \
+  }
+
+#define TEST_ALL()                                                             \
+  TEST_TYPE (int16_t, int8_t)                                                  \
+  TEST_TYPE (uint16_t, uint8_t)                                                \
+  TEST_TYPE (int32_t, int16_t)                                                 \
+  TEST_TYPE (uint32_t, uint16_t)                                               \
+  TEST_TYPE (int64_t, int32_t)                                                 \
+  TEST_TYPE (uint64_t, uint32_t)                                               \
+  TEST_TYPE (float, _Float16)                                                  \
+  TEST_TYPE (double, float)
+
+TEST_ALL ()
+
+/* { dg-final { scan-assembler-times {\tvwadd\.vv} 9 } } */
+/* { dg-final { scan-assembler-times {\tvwaddu\.vv} 9 } } */
+/* { dg-final { scan-assembler-times {\tvfwadd\.vv} 6 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c
new file mode 100644 (file)
index 0000000..f8fdebb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-2.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE1, TYPE2)                                                \
+  __attribute__ ((noipa)) void vwadd_##TYPE1_##TYPE2 (                         \
+    TYPE1 *__restrict dst, TYPE1 *__restrict dst2, TYPE1 *__restrict dst3,     \
+    TYPE2 *__restrict a, TYPE2 *__restrict b, TYPE2 *__restrict a2,            \
+    TYPE2 *__restrict b2, int *__restrict pred, int n)                         \
+  {                                                                            \
+    for (int i = 0; i < n; i++)                                                \
+      {                                                                        \
+       dst[i] = pred[i] ? (TYPE1) a[i] - (TYPE1) b[i] : dst[i];               \
+       dst2[i] = pred[i] ? (TYPE1) a2[i] - (TYPE1) b[i] : dst2[i];            \
+       dst3[i] = pred[i] ? (TYPE1) a2[i] - (TYPE1) a[i] : dst3[i];            \
+      }                                                                        \
+  }
+
+#define TEST_ALL()                                                             \
+  TEST_TYPE (int16_t, int8_t)                                                  \
+  TEST_TYPE (uint16_t, uint8_t)                                                \
+  TEST_TYPE (int32_t, int16_t)                                                 \
+  TEST_TYPE (uint32_t, uint16_t)                                               \
+  TEST_TYPE (int64_t, int32_t)                                                 \
+  TEST_TYPE (uint64_t, uint32_t)                                               \
+  TEST_TYPE (float, _Float16)                                                  \
+  TEST_TYPE (double, float)
+
+TEST_ALL ()
+
+/* { dg-final { scan-assembler-times {\tvwsub\.vv} 9 } } */
+/* { dg-final { scan-assembler-times {\tvwsubu\.vv} 9 } } */
+/* { dg-final { scan-assembler-times {\tvfwsub\.vv} 6 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c
new file mode 100644 (file)
index 0000000..ef61a4f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-3.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE1, TYPE2)                                                \
+  __attribute__ ((noipa)) void vwadd_##TYPE1_##TYPE2 (                         \
+    TYPE1 *__restrict dst, TYPE1 *__restrict dst2, TYPE1 *__restrict dst3,     \
+    TYPE1 *__restrict dst4, TYPE2 *__restrict a, TYPE2 *__restrict b,          \
+    TYPE2 *__restrict a2, TYPE2 *__restrict b2, int *__restrict pred, int n)   \
+  {                                                                            \
+    for (int i = 0; i < n; i++)                                                \
+      {                                                                        \
+       dst[i] = pred[i] ? (TYPE1) a[i] * (TYPE1) b[i] : dst[i];               \
+       dst2[i] = pred[i] ? (TYPE1) a2[i] * (TYPE1) b[i] : dst2[i];            \
+       dst3[i] = pred[i] ? (TYPE1) a2[i] * (TYPE1) a[i] : dst3[i];            \
+       dst4[i] = pred[i] ? (TYPE1) a[i] * (TYPE1) b2[i] : dst4[i];            \
+      }                                                                        \
+  }
+
+#define TEST_ALL()                                                             \
+  TEST_TYPE (int16_t, int8_t)                                                  \
+  TEST_TYPE (uint16_t, uint8_t)                                                \
+  TEST_TYPE (int32_t, int16_t)                                                 \
+  TEST_TYPE (uint32_t, uint16_t)                                               \
+  TEST_TYPE (int64_t, int32_t)                                                 \
+  TEST_TYPE (uint64_t, uint32_t)                                               \
+  TEST_TYPE (float, _Float16)                                                  \
+  TEST_TYPE (double, float)
+
+TEST_ALL ()
+
+/* { dg-final { scan-assembler-times {\tvwmul\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvwmulu\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvfwmul\.vv} 8 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c
new file mode 100644 (file)
index 0000000..9aa6355
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-4.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */
+
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE1, TYPE2, TYPE3)                                         \
+  __attribute__ ((noipa)) void vwadd_##TYPE1_##TYPE2 (                         \
+    TYPE1 *__restrict dst, TYPE1 *__restrict dst2, TYPE1 *__restrict dst3,     \
+    TYPE1 *__restrict dst4, TYPE2 *__restrict a, TYPE3 *__restrict b,          \
+    TYPE3 *__restrict a2, TYPE2 *__restrict b2, int *__restrict pred, int n)   \
+  {                                                                            \
+    for (int i = 0; i < n; i++)                                                \
+      {                                                                        \
+       dst[i] = pred[i] ? (TYPE1) a[i] * (TYPE1) b[i] : dst[i];               \
+       dst2[i] = pred[i] ? (TYPE1) a2[i] * (TYPE1) b[i] : dst2[i];            \
+       dst3[i] = pred[i] ? (TYPE1) a2[i] * (TYPE1) a[i] : dst3[i];            \
+       dst4[i] = pred[i] ? (TYPE1) a[i] * (TYPE1) b2[i] : dst4[i];            \
+      }                                                                        \
+  }
+
+#define TEST_ALL()                                                             \
+  TEST_TYPE (int16_t, int8_t, uint8_t)                                         \
+  TEST_TYPE (int32_t, int16_t, uint16_t)                                       \
+  TEST_TYPE (int64_t, int32_t, uint32_t)                                       \
+  TEST_TYPE (int16_t, uint8_t, int8_t)                                         \
+  TEST_TYPE (int32_t, uint16_t, int16_t)                                       \
+  TEST_TYPE (int64_t, uint32_t, int32_t)
+
+TEST_ALL ()
+
+/* { dg-final { scan-assembler-times {\tvwmulsu\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvwmul\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvwmulu\.vv} 6 } } */
+/* { dg-final { scan-assembler-not {\tvmul} } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c
new file mode 100644 (file)
index 0000000..efbd3d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-5.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE1, TYPE2)                                                \
+  __attribute__ ((noipa)) void vwadd_##TYPE1_##TYPE2 (                         \
+    TYPE1 *__restrict dst, TYPE1 *__restrict dst2, TYPE1 *__restrict dst3,     \
+    TYPE1 *__restrict dst4, TYPE2 *__restrict a, TYPE2 *__restrict b,          \
+    TYPE2 *__restrict a2, TYPE2 *__restrict b2, int *__restrict pred, int n)   \
+  {                                                                            \
+    for (int i = 0; i < n; i++)                                                \
+      if (pred[i])                                                             \
+       {                                                                      \
+         dst[i] += (TYPE1) a[i] * (TYPE1) b[i];                               \
+         dst2[i] += (TYPE1) a2[i] * (TYPE1) b[i];                             \
+         dst3[i] += (TYPE1) a2[i] * (TYPE1) a[i];                             \
+         dst4[i] += (TYPE1) a[i] * (TYPE1) b2[i];                             \
+       }                                                                      \
+  }
+
+#define TEST_ALL()                                                             \
+  TEST_TYPE (int16_t, int8_t)                                                  \
+  TEST_TYPE (uint16_t, uint8_t)                                                \
+  TEST_TYPE (int32_t, int16_t)                                                 \
+  TEST_TYPE (uint32_t, uint16_t)                                               \
+  TEST_TYPE (int64_t, int32_t)                                                 \
+  TEST_TYPE (uint64_t, uint32_t)                                               \
+  TEST_TYPE (float, _Float16)                                                  \
+  TEST_TYPE (double, float)
+
+TEST_ALL ()
+
+/* { dg-final { scan-assembler-times {\tvwmacc\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvwmaccu\.vv} 12 } } */
+/* { dg-final { scan-assembler-times {\tvfwmacc\.vv} 8 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c
new file mode 100644 (file)
index 0000000..083571c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-6.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */
+
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE1, TYPE2, TYPE3)                                         \
+  __attribute__ ((noipa)) void vwadd_##TYPE1_##TYPE2 (                         \
+    TYPE1 *__restrict dst, TYPE1 *__restrict dst2, TYPE1 *__restrict dst3,     \
+    TYPE1 *__restrict dst4, TYPE2 *__restrict a, TYPE3 *__restrict b,          \
+    TYPE3 *__restrict a2, TYPE2 *__restrict b2, int *__restrict pred, int n)   \
+  {                                                                            \
+    for (int i = 0; i < n; i++)                                                \
+      if (pred[i])                                                             \
+       {                                                                      \
+         dst[i] += (TYPE1) a[i] * (TYPE1) b[i];                               \
+         dst2[i] += (TYPE1) a2[i] * (TYPE1) b[i];                             \
+         dst3[i] += (TYPE1) a2[i] * (TYPE1) a[i];                             \
+         dst4[i] += (TYPE1) a[i] * (TYPE1) b2[i];                             \
+       }                                                                      \
+  }
+
+#define TEST_ALL()                                                             \
+  TEST_TYPE (int16_t, int8_t, uint8_t)                                         \
+  TEST_TYPE (int32_t, int16_t, uint16_t)                                       \
+  TEST_TYPE (int64_t, int32_t, uint32_t)
+
+TEST_ALL ()
+
+/* { dg-final { scan-assembler-times {\tvwmaccsu\.vv} 6 } } */
+/* { dg-final { scan-assembler-times {\tvwmacc\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvwmaccu\.vv} 3 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c
new file mode 100644 (file)
index 0000000..41017c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-7.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE1, TYPE2)                                                \
+  __attribute__ ((noipa)) void vwadd_##TYPE1_##TYPE2 (                         \
+    TYPE1 *__restrict dst, TYPE1 *__restrict dst2, TYPE1 *__restrict dst3,     \
+    TYPE1 *__restrict dst4, TYPE2 *__restrict a, TYPE2 *__restrict b,          \
+    TYPE2 *__restrict a2, TYPE2 *__restrict b2, int *__restrict pred, int n)   \
+  {                                                                            \
+    for (int i = 0; i < n; i++)                                                \
+      if (pred[i])                                                             \
+       {                                                                      \
+         dst[i] += -((TYPE1) a[i] * (TYPE1) b[i]);                            \
+         dst2[i] += -((TYPE1) a2[i] * (TYPE1) b[i]);                          \
+         dst3[i] += -((TYPE1) a2[i] * (TYPE1) a[i]);                          \
+         dst4[i] += -((TYPE1) a[i] * (TYPE1) b2[i]);                          \
+       }                                                                      \
+  }
+
+#define TEST_ALL()                                                             \
+  TEST_TYPE (float, _Float16)                                                  \
+  TEST_TYPE (double, float)
+
+TEST_ALL ()
+
+/* { dg-final { scan-assembler-times {\tvfwnmsac\.vv} 8 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c
new file mode 100644 (file)
index 0000000..8aea32d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-8.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE1, TYPE2)                                                \
+  __attribute__ ((noipa)) void vwadd_##TYPE1_##TYPE2 (                         \
+    TYPE1 *__restrict dst, TYPE1 *__restrict dst2, TYPE1 *__restrict dst3,     \
+    TYPE1 *__restrict dst4, TYPE2 *__restrict a, TYPE2 *__restrict b,          \
+    TYPE2 *__restrict a2, TYPE2 *__restrict b2, int *__restrict pred, int n)   \
+  {                                                                            \
+    for (int i = 0; i < n; i++)                                                \
+      {                                                                        \
+       dst[i] = pred[i] ? (TYPE1) a[i] * (TYPE1) b[i] - dst[i] : dst[i];      \
+       dst2[i] = pred[i] ? (TYPE1) a2[i] * (TYPE1) b[i] - dst2[i] : dst2[i];  \
+       dst3[i] = pred[i] ? (TYPE1) a2[i] * (TYPE1) a[i] - dst3[i] : dst3[i];  \
+       dst4[i] = pred[i] ? (TYPE1) a[i] * (TYPE1) b2[i] - dst4[i] : dst4[i];  \
+      }                                                                        \
+  }
+
+#define TEST_ALL()                                                             \
+  TEST_TYPE (float, _Float16)                                                  \
+  TEST_TYPE (double, float)
+
+TEST_ALL ()
+
+/* { dg-final { scan-assembler-times {\tvfwmsac\.vv} 8 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c
new file mode 100644 (file)
index 0000000..9e32211
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_widen_complicate-9.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -ffast-math" } */
+
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE1, TYPE2)                                                \
+  __attribute__ ((noipa)) void vwadd_##TYPE1_##TYPE2 (                         \
+    TYPE1 *__restrict dst, TYPE1 *__restrict dst2, TYPE1 *__restrict dst3,     \
+    TYPE1 *__restrict dst4, TYPE2 *__restrict a, TYPE2 *__restrict b,          \
+    TYPE2 *__restrict a2, TYPE2 *__restrict b2, int *__restrict pred, int n)   \
+  {                                                                            \
+    for (int i = 0; i < n; i++)                                                \
+      {                                                                        \
+       dst[i] = pred[i] ? -((TYPE1) a[i] * (TYPE1) b[i]) - dst[i] : dst[i];   \
+       dst2[i]                                                                \
+         = pred[i] ? -((TYPE1) a2[i] * (TYPE1) b[i]) - dst2[i] : dst2[i];     \
+       dst3[i]                                                                \
+         = pred[i] ? -((TYPE1) a2[i] * (TYPE1) a[i]) - dst3[i] : dst3[i];     \
+       dst4[i]                                                                \
+         = pred[i] ? -((TYPE1) a[i] * (TYPE1) b2[i]) - dst4[i] : dst4[i];     \
+      }                                                                        \
+  }
+
+#define TEST_ALL()                                                             \
+  TEST_TYPE (float, _Float16)                                                  \
+  TEST_TYPE (double, float)
+
+TEST_ALL ()
+
+/* Other optimization removed some mask operand of vfwnmacc.vv, so expected 6
+ * instead of 8.  */
+/* { dg-final { scan-assembler-times {\tvfwnmacc\.vv\t} 6 } } */
+/* { dg-final { scan-assembler-not {\tvmerge\.vvm\t} } } */