arm64: dts: imx8dxl/qm/qxp: Add Root Port node and PERST property

Since describing the PCIe PERST# property under Host Bridge node is now
deprecated, it is recommended to add it to the Root Port node, so
creating the Root Port node and add the reset-gpios property in Root
Port.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
index 469de8b536b5866ea83cc0542941039996ae5f23..009990b2e5590435f4f74f32cd02d4cc91437cc7 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
@@ -78,6 +78,17 @@ hsio_subsys: bus@5f000000 {
                power-domains = <&pd IMX_SC_R_PCIE_B>;
                fsl,max-link-speed = <3>;
                status = "disabled";
+
+               pcieb_port0: pcie@0 {
+                       compatible = "pciclass,0604";
+                       device_type = "pci";
+                       reg = <0x0 0x0 0x0 0x0 0x0>;
+                       bus-range = <0x01 0xff>;
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       ranges;
+               };
        };
 
        pcieb_ep: pcie-ep@5f010000 {

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
index 441e009030299418d90cb961c88e8ee711255b6d..78e8d41e67916221aa019756e5bea41677af78ed 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -675,6 +675,7 @@
        phy-names = "pcie-phy";
        pinctrl-0 = <&pinctrl_pcieb>;
        pinctrl-names = "default";
+       /* This property is deprecated, use reset-gpios from the Root Port node. */
        reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
        vpcie-supply = <&reg_pcieb>;
        vpcie3v3aux-supply = <&reg_pcieb>;
@@ -689,6 +690,10 @@
        status = "disabled";
 };
 
+&pcieb_port0 {
+       reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
+};
+
 &sai0 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_sai0>;

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index 011a89d85961d98925785a8a2f5156cf1b45422d..f706c86137c0f7278931e4150d19505eb3ae5551 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
@@ -810,6 +810,7 @@
        phy-names = "pcie-phy";
        pinctrl-0 = <&pinctrl_pciea>;
        pinctrl-names = "default";
+       /* This property is deprecated, use reset-gpios from the Root Port node. */
        reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;
        vpcie-supply = <&reg_pciea>;
        vpcie3v3aux-supply = <&reg_pciea>;
@@ -817,15 +818,24 @@
        status = "okay";
 };
 
+&pciea_port0 {
+       reset-gpios = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;
+};
+
 &pcieb {
        phys = <&hsio_phy 1 PHY_TYPE_PCIE 1>;
        phy-names = "pcie-phy";
        pinctrl-0 = <&pinctrl_pcieb>;
        pinctrl-names = "default";
+       /* This property is deprecated, use reset-gpios from the Root Port node. */
        reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;
        status = "disabled";
 };
 
+&pcieb_port0 {
+       reset-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;
+};
+
 &qm_pwm_lvds0 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pwm_lvds0>;

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
index f2c94cdb682b9c4a7cd0fda35ca86c159bdfa937..2e4fbfe0ca16af4ee02806943e10d49a0bc65754 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
@@ -41,6 +41,17 @@
                power-domains = <&pd IMX_SC_R_PCIE_A>;
                fsl,max-link-speed = <3>;
                status = "disabled";
+
+               pciea_port0: pcie@0 {
+                       compatible = "pciclass,0604";
+                       device_type = "pci";
+                       reg = <0x0 0x0 0x0 0x0 0x0>;
+                       bus-range = <0x01 0xff>;
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       ranges;
+               };
        };
 
        pcie0_ep: pciea_ep: pcie-ep@5f000000 {
@@ -91,6 +102,17 @@
                power-domains = <&pd IMX_SC_R_PCIE_B>;
                fsl,max-link-speed = <3>;
                status = "disabled";
+
+               pcieb_port0: pcie@0 {
+                       compatible = "pciclass,0604";
+                       device_type = "pci";
+                       reg = <0x0 0x0 0x0 0x0 0x0>;
+                       bus-range = <0x01 0xff>;
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       ranges;
+               };
        };
 
        sata: sata@5f020000 {

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index c07138055229c7ae94142112f6e4e25c60c1fe7e..2af32eca612aa910f15494a5b75e2e2b4f42cee6 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -730,6 +730,7 @@
        phy-names = "pcie-phy";
        pinctrl-0 = <&pinctrl_pcieb>;
        pinctrl-names = "default";
+       /* This property is deprecated, use reset-gpios from the Root Port node. */
        reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
        vpcie-supply = <&reg_pcieb>;
        vpcie3v3aux-supply = <&reg_pcieb>;
@@ -745,6 +746,10 @@
        status = "disabled";
 };
 
+&pcieb_port0 {
+       reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
+};
+
 &scu_key {
        status = "okay";
 };