drm/xe/gsc: Add debugfs to print GSC info

This is useful for debug, in case something goes wrong with the GSC. The
info includes the version information and the current value of the HECI1
status registers.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: Julia Filipchuk <julia.filipchuk@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240828215158.2743994-5-daniele.ceraolospurio@intel.com

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index b9670ae09a9ef967ec061cf3f02b348b0481c3cb..edfd812e0f41745cdee2ecb3068ae01afac175d3 100644 (file)
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -40,6 +40,7 @@ xe-y += xe_bb.o \
        xe_ggtt.o \
        xe_gpu_scheduler.o \
        xe_gsc.o \
+       xe_gsc_debugfs.o \
        xe_gsc_proxy.o \
        xe_gsc_submit.o \
        xe_gt.o \

diff --git a/drivers/gpu/drm/xe/regs/xe_gsc_regs.h b/drivers/gpu/drm/xe/regs/xe_gsc_regs.h
index e2a925be137cd33dc32c89687d8f37ad6b23924f..7702364b65f1ad97b6bfba4cf0909e6235cbcbc9 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gsc_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gsc_regs.h
@@ -32,8 +32,12 @@
 #define   HECI1_FWSTS1_CURRENT_STATE_RESET             0
 #define   HECI1_FWSTS1_PROXY_STATE_NORMAL              5
 #define   HECI1_FWSTS1_INIT_COMPLETE                   REG_BIT(9)
+#define HECI_FWSTS2(base)                              XE_REG((base) + 0xc48)
+#define HECI_FWSTS3(base)                              XE_REG((base) + 0xc60)
+#define HECI_FWSTS4(base)                              XE_REG((base) + 0xc64)
 #define HECI_FWSTS5(base)                              XE_REG((base) + 0xc68)
 #define   HECI1_FWSTS5_HUC_AUTH_DONE                   REG_BIT(19)
+#define HECI_FWSTS6(base)                              XE_REG((base) + 0xc6c)
 
 #define HECI_H_GS1(base)       XE_REG((base) + 0xc4c)
 #define   HECI_H_GS1_ER_PREP   REG_BIT(0)

diff --git a/drivers/gpu/drm/xe/xe_gsc.c b/drivers/gpu/drm/xe/xe_gsc.c
index 50ff43f5426aa5c654d18fc28bbc615098734adb..648786afffe05a120cd707818cc8a258b1d21252 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gsc.c
+++ b/drivers/gpu/drm/xe/xe_gsc.c
@@ -8,6 +8,7 @@
 #include <linux/delay.h>
 
 #include <drm/drm_managed.h>
+#include <drm/drm_print.h>
 
 #include <generated/xe_wa_oob.h>
 
@@ -587,3 +588,35 @@ void xe_gsc_wa_14015076503(struct xe_gt *gt, bool prep)
                msleep(200);
        }
 }
+
+/**
+ * xe_gsc_print_info - print info about GSC FW status
+ * @gsc: the GSC structure
+ * @p: the printer to be used to print the info
+ */
+void xe_gsc_print_info(struct xe_gsc *gsc, struct drm_printer *p)
+{
+       struct xe_gt *gt = gsc_to_gt(gsc);
+       int err;
+
+       xe_uc_fw_print(&gsc->fw, p);
+
+       drm_printf(p, "\tfound security version %u\n", gsc->security_version);
+
+       if (!xe_uc_fw_is_enabled(&gsc->fw))
+               return;
+
+       err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GSC);
+       if (err)
+               return;
+
+       drm_printf(p, "\nHECI1 FWSTS: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
+                       xe_mmio_read32(gt, HECI_FWSTS1(MTL_GSC_HECI1_BASE)),
+                       xe_mmio_read32(gt, HECI_FWSTS2(MTL_GSC_HECI1_BASE)),
+                       xe_mmio_read32(gt, HECI_FWSTS3(MTL_GSC_HECI1_BASE)),
+                       xe_mmio_read32(gt, HECI_FWSTS4(MTL_GSC_HECI1_BASE)),
+                       xe_mmio_read32(gt, HECI_FWSTS5(MTL_GSC_HECI1_BASE)),
+                       xe_mmio_read32(gt, HECI_FWSTS6(MTL_GSC_HECI1_BASE)));
+
+       xe_force_wake_put(gt_to_fw(gt), XE_FW_GSC);
+}

diff --git a/drivers/gpu/drm/xe/xe_gsc.h b/drivers/gpu/drm/xe/xe_gsc.h
index 1c7a623faf1114cfb637d61fad2b428bf36cddaf..e282b9ef6ec4d5b4956bb5ffdb0ccb1d328b0d19 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gsc.h
+++ b/drivers/gpu/drm/xe/xe_gsc.h
@@ -8,6 +8,7 @@
 
 #include <linux/types.h>
 
+struct drm_printer;
 struct xe_gsc;
 struct xe_gt;
 struct xe_hw_engine;
@@ -21,4 +22,6 @@ void xe_gsc_hwe_irq_handler(struct xe_hw_engine *hwe, u16 intr_vec);
 
 void xe_gsc_wa_14015076503(struct xe_gt *gt, bool prep);
 
+void xe_gsc_print_info(struct xe_gsc *gsc, struct drm_printer *p);
+
 #endif

diff --git a/drivers/gpu/drm/xe/xe_gsc_debugfs.c b/drivers/gpu/drm/xe/xe_gsc_debugfs.c
new file mode 100644 (file)
index 0000000..461d7e9
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_gsc_debugfs.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include "xe_gsc_debugfs.h"
+
+#include <drm/drm_debugfs.h>
+#include <drm/drm_managed.h>
+
+#include "xe_device.h"
+#include "xe_gt.h"
+#include "xe_gsc.h"
+#include "xe_macros.h"
+#include "xe_pm.h"
+
+static struct xe_gt *
+gsc_to_gt(struct xe_gsc *gsc)
+{
+       return container_of(gsc, struct xe_gt, uc.gsc);
+}
+
+static struct xe_device *
+gsc_to_xe(struct xe_gsc *gsc)
+{
+       return gt_to_xe(gsc_to_gt(gsc));
+}
+
+static struct xe_gsc *node_to_gsc(struct drm_info_node *node)
+{
+       return node->info_ent->data;
+}
+
+static int gsc_info(struct seq_file *m, void *data)
+{
+       struct xe_gsc *gsc = node_to_gsc(m->private);
+       struct xe_device *xe = gsc_to_xe(gsc);
+       struct drm_printer p = drm_seq_file_printer(m);
+
+       xe_pm_runtime_get(xe);
+       xe_gsc_print_info(gsc, &p);
+       xe_pm_runtime_put(xe);
+
+       return 0;
+}
+
+static const struct drm_info_list debugfs_list[] = {
+       {"gsc_info", gsc_info, 0},
+};
+
+void xe_gsc_debugfs_register(struct xe_gsc *gsc, struct dentry *parent)
+{
+       struct drm_minor *minor = gsc_to_xe(gsc)->drm.primary;
+       struct drm_info_list *local;
+       int i;
+
+#define DEBUGFS_SIZE   (ARRAY_SIZE(debugfs_list) * sizeof(struct drm_info_list))
+       local = drmm_kmalloc(&gsc_to_xe(gsc)->drm, DEBUGFS_SIZE, GFP_KERNEL);
+       if (!local)
+               return;
+
+       memcpy(local, debugfs_list, DEBUGFS_SIZE);
+#undef DEBUGFS_SIZE
+
+       for (i = 0; i < ARRAY_SIZE(debugfs_list); ++i)
+               local[i].data = gsc;
+
+       drm_debugfs_create_files(local,
+                                ARRAY_SIZE(debugfs_list),
+                                parent, minor);
+}

diff --git a/drivers/gpu/drm/xe/xe_gsc_debugfs.h b/drivers/gpu/drm/xe/xe_gsc_debugfs.h
new file mode 100644 (file)
index 0000000..c2e2645
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_gsc_debugfs.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef _XE_GSC_DEBUGFS_H_
+#define _XE_GSC_DEBUGFS_H_
+
+struct dentry;
+struct xe_gsc;
+
+void xe_gsc_debugfs_register(struct xe_gsc *gsc, struct dentry *parent);
+
+#endif

diff --git a/drivers/gpu/drm/xe/xe_uc_debugfs.c b/drivers/gpu/drm/xe/xe_uc_debugfs.c
index 78eb8db737910b747d6494a7334f2c2668e60c59..24a4209051eecd6668e1b5aa424383347aa091c0 100644 (file)
--- a/drivers/gpu/drm/xe/xe_uc_debugfs.c
+++ b/drivers/gpu/drm/xe/xe_uc_debugfs.c
@@ -8,6 +8,7 @@
 #include <drm/drm_debugfs.h>
 
 #include "xe_gt.h"
+#include "xe_gsc_debugfs.h"
 #include "xe_guc_debugfs.h"
 #include "xe_huc_debugfs.h"
 #include "xe_macros.h"
@@ -23,6 +24,7 @@ void xe_uc_debugfs_register(struct xe_uc *uc, struct dentry *parent)
                return;
        }
 
+       xe_gsc_debugfs_register(&uc->gsc, root);
        xe_guc_debugfs_register(&uc->guc, root);
        xe_huc_debugfs_register(&uc->huc, root);
 }