return HFLIP;
case V4L2_CID_VFLIP:
return VFLIP;
+ case V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE:
+ return IR_TYPE;
+ case V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD:
+ return IR_PERIOD;
default:
return INST_FW_CAP_MAX;
}
return V4L2_CID_HFLIP;
case VFLIP:
return V4L2_CID_VFLIP;
+ case IR_TYPE:
+ return V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE;
+ case IR_PERIOD:
+ return V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD;
default:
return 0;
}
&hfi_val, sizeof(u32));
}
+int iris_set_ir_period(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id)
+{
+ const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
+ struct vb2_queue *q = v4l2_m2m_get_dst_vq(inst->m2m_ctx);
+ u32 ir_period = inst->fw_caps[cap_id].value;
+ u32 ir_type = 0;
+
+ if (inst->fw_caps[IR_TYPE].value ==
+ V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM) {
+ if (vb2_is_streaming(q))
+ return 0;
+ ir_type = HFI_PROP_IR_RANDOM_PERIOD;
+ } else if (inst->fw_caps[IR_TYPE].value ==
+ V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC) {
+ ir_type = HFI_PROP_IR_CYCLIC_PERIOD;
+ } else {
+ return -EINVAL;
+ }
+
+ return hfi_ops->session_set_property(inst, ir_type,
+ HFI_HOST_FLAGS_NONE,
+ iris_get_port_info(inst, cap_id),
+ HFI_PAYLOAD_U32,
+ &ir_period, sizeof(u32));
+}
+
int iris_set_properties(struct iris_inst *inst, u32 plane)
{
const struct iris_hfi_command_ops *hfi_ops = inst->core->hfi_ops;
int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
int iris_set_rotation(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
int iris_set_flip(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
+int iris_set_ir_period(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id);
int iris_set_properties(struct iris_inst *inst, u32 plane);
#endif
#define HFI_PROP_QP_PACKED 0x0300012e
#define HFI_PROP_MIN_QP_PACKED 0x0300012f
#define HFI_PROP_MAX_QP_PACKED 0x03000130
+#define HFI_PROP_IR_RANDOM_PERIOD 0x03000131
#define HFI_PROP_TOTAL_BITRATE 0x0300013b
#define HFI_PROP_MAX_GOP_FRAMES 0x03000146
#define HFI_PROP_MAX_B_FRAMES 0x03000147
#define HFI_PROP_AV1_FILM_GRAIN_PRESENT 0x03000180
#define HFI_PROP_AV1_SUPER_BLOCK_ENABLED 0x03000181
#define HFI_PROP_AV1_OP_POINT 0x03000182
+#define HFI_PROP_IR_CYCLIC_PERIOD 0x0300017E
#define HFI_PROP_OPB_ENABLE 0x03000184
#define HFI_PROP_AV1_TILE_ROWS_COLUMNS 0x03000187
#define HFI_PROP_AV1_DRAP_CONFIG 0x03000189
ROTATION,
HFLIP,
VFLIP,
+ IR_TYPE,
+ IR_PERIOD,
INST_FW_CAP_MAX,
};
CAP_FLAG_DYNAMIC_ALLOWED,
.set = iris_set_flip,
},
+ {
+ .cap_id = IR_TYPE,
+ .min = V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM,
+ .max = V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC,
+ .step_or_mask = BIT(V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM) |
+ BIT(V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC),
+ .value = V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM,
+ .flags = CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
+ },
+ {
+ .cap_id = IR_PERIOD,
+ .min = 0,
+ .max = INT_MAX,
+ .step_or_mask = 1,
+ .value = 0,
+ .flags = CAP_FLAG_OUTPUT_PORT |
+ CAP_FLAG_DYNAMIC_ALLOWED,
+ .set = iris_set_ir_period,
+ },
};
static struct platform_inst_caps platform_inst_cap_sm8550 = {