drm/msm/a8xx: Add perfcntr flush sequence

With the slice architecture, we need to flush the slice and unslice
counters to perf RAM before reading counters.

Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com>
Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/728216/
Message-ID: <20260526145137.160554-13-robin.clark@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index e47fa2cdc314383b779415df3dbbfe161b03dc85..2178b496097951e59122303976a05cbb69072892 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2843,6 +2843,7 @@ const struct adreno_gpu_funcs a8xx_gpu_funcs = {
                .progress = a8xx_progress,
                .sysprof_setup = a6xx_gmu_sysprof_setup,
                .perfcntr_configure = a6xx_perfcntr_configure,
+               .perfcntr_flush = a8xx_perfcntr_flush,
        },
        .init = a6xx_gpu_init,
        .get_timestamp = a8xx_gmu_get_timestamp,

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index 99c3e55f5ca8fcc73cbef065f391d5bb73c9c8ee..3491a24a9320b967b3e3b64c43c7e8501fd29581 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -334,5 +334,6 @@ void a8xx_preempt_hw_init(struct msm_gpu *gpu);
 void a8xx_preempt_trigger(struct msm_gpu *gpu);
 void a8xx_preempt_irq(struct msm_gpu *gpu);
 bool a8xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
+void a8xx_perfcntr_flush(struct msm_gpu *gpu);
 void a8xx_recover(struct msm_gpu *gpu);
 #endif /* __A6XX_GPU_H__ */

diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
index f29cd6e1fde06c5d9fb784bbc1671d4ff13c6b59..3adf250305485374a34f8d6968ff70068d4043f8 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
@@ -1346,3 +1346,23 @@ bool a8xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
 {
        return true;
 }
+
+void a8xx_perfcntr_flush(struct msm_gpu *gpu)
+{
+       u32 val;
+
+       /*
+        * Flush delta counters (both perf counters and pipe stats) present in
+        * RBBM_S and RBBM_US to perf RAM logic to get the latest data.
+        */
+       gpu_write(gpu, REG_A8XX_RBBM_PERFCTR_FLUSH_HOST_CMD, BIT(0));
+       gpu_write(gpu, REG_A8XX_RBBM_SLICE_PERFCTR_FLUSH_HOST_CMD, BIT(0));
+
+       /* Ensure all writes are posted before polling status register */
+       wmb();
+
+       if (gpu_poll_timeout(gpu, REG_A8XX_RBBM_PERFCTR_FLUSH_HOST_STATUS, val,
+                            val & BIT(0), 100, 100 * 1000)) {
+               dev_err(&gpu->pdev->dev, "Perfcounter flush timed out: status=0x%08x\n", val);
+       }
+}