Handle shift amounts 0..31. It is unclear why the shift amounts

were initially restricted to 0..3.

git-svn-id: svn://svn.valgrind.org/vex/trunk@3206

diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c
index e0c0458d48f7aa5c0245e6e34883c2dda7562a4e..5260c990877ec0f34657c64e14cc50f4b984a8db 100644 (file)
--- a/VEX/priv/guest_arm_toIR.c
+++ b/VEX/priv/guest_arm_toIR.c
@@ -19665,10 +19665,10 @@ DisResult disInstr_THUMB_WRK (
       UInt how  = INSN1(5,4);
 
       Bool valid = !isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM);
-      /* but allow "add.w reg, sp, reg, lsl #N for N=0,1,2 or 3
+      /* but allow "add.w reg, sp, reg, lsl #N for N=0..31
          (T3) "ADD (SP plus register) */
       if (!valid && INSN0(8,5) == BITS4(1,0,0,0) // add
-          && rD != 15 && rN == 13 && imm5 <= 3 && how == 0) {
+          && rD != 15 && rN == 13 && imm5 <= 31 && how == 0) {
          valid = True;
       }
       /* also allow "sub.w reg, sp, reg   w/ no shift