net/mlx5: Expose IFC bits for TPH

Expose IFC bits for the TPH functionality.

Signed-off-by: Yishai Hadas <yishaih@nvidia.com>
Reviewed-by: Edward Srouji <edwards@nvidia.com>
Reviewed-by: Moshe Shemesh <moshe@nvidia.com>
Link: https://patch.msgid.link/38ea3a0d56551364214e8edf359c9c77c9a3b71b.1752752567.git.leon@kernel.org
Signed-off-by: Leon Romanovsky <leon@kernel.org>

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index ed4130e49c275bc90e164277548e981b6da355e0..8360d9011d4ff1073bd78888e65abaa8945fcafd 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -1871,7 +1871,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         reserved_at_280[0x10];
        u8         max_wqe_sz_sq[0x10];
 
-       u8         reserved_at_2a0[0xb];
+       u8         reserved_at_2a0[0x7];
+       u8         mkey_pcie_tph[0x1];
+       u8         reserved_at_2a8[0x3];
        u8         shampo[0x1];
        u8         reserved_at_2ac[0x4];
        u8         max_wqe_sz_rq[0x10];
@@ -4418,6 +4420,10 @@ enum {
        MLX5_MKC_ACCESS_MODE_CROSSING = 0x6,
 };
 
+enum {
+       MLX5_MKC_PCIE_TPH_NO_STEERING_TAG_INDEX = 0,
+};
+
 struct mlx5_ifc_mkc_bits {
        u8         reserved_at_0[0x1];
        u8         free[0x1];
@@ -4469,7 +4475,11 @@ struct mlx5_ifc_mkc_bits {
        u8         relaxed_ordering_read[0x1];
        u8         log_page_size[0x6];
 
-       u8         reserved_at_1e0[0x20];
+       u8         reserved_at_1e0[0x5];
+       u8         pcie_tph_en[0x1];
+       u8         pcie_tph_ph[0x2];
+       u8         pcie_tph_steering_tag_index[0x8];
+       u8         reserved_at_1f0[0x10];
 };
 
 struct mlx5_ifc_pkey_bits {