drop drm-i915-fix-tlb-invalidation-for-gen12-video-and-compute-engines.patch from...

diff --git a/queue-5.10/drm-i915-fix-tlb-invalidation-for-gen12-video-and-compute-engines.patch b/queue-5.10/drm-i915-fix-tlb-invalidation-for-gen12-video-and-compute-engines.patch
deleted file mode 100644 (file)
index 021548c..0000000
--- a/queue-5.10/drm-i915-fix-tlb-invalidation-for-gen12-video-and-compute-engines.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 04aa64375f48a5d430b5550d9271f8428883e550 Mon Sep 17 00:00:00 2001
-From: Andrzej Hajda <andrzej.hajda@intel.com>
-Date: Mon, 14 Nov 2022 11:38:24 +0100
-Subject: drm/i915: fix TLB invalidation for Gen12 video and compute engines
-
-From: Andrzej Hajda <andrzej.hajda@intel.com>
-
-commit 04aa64375f48a5d430b5550d9271f8428883e550 upstream.
-
-In case of Gen12 video and compute engines, TLB_INV registers are masked -
-to modify one bit, corresponding bit in upper half of the register must
-be enabled, otherwise nothing happens.
-
-CVE: CVE-2022-4139
-Suggested-by: Chris Wilson <chris.p.wilson@intel.com>
-Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
-Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
-Cc: stable@vger.kernel.org
-Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/gpu/drm/i915/gt/intel_gt.c |    5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/drivers/gpu/drm/i915/gt/intel_gt.c
-+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
-@@ -745,6 +745,11 @@ void intel_gt_invalidate_tlbs(struct int
-               if (!i915_mmio_reg_offset(rb.reg))
-                       continue;
- 
-+              if (GRAPHICS_VER(i915) == 12 && (engine->class == VIDEO_DECODE_CLASS ||
-+                  engine->class == VIDEO_ENHANCEMENT_CLASS ||
-+                  engine->class == COMPUTE_CLASS))
-+                      rb.bit = _MASKED_BIT_ENABLE(rb.bit);
-+
-               intel_uncore_write_fw(uncore, rb.reg, rb.bit);
-       }
- 

diff --git a/queue-5.10/series b/queue-5.10/series
index b85d60375cf84fe7049d80612bd513c6828477b2..8a0f25dcb34d04afec006be623f43cf9551ca0e6 100644 (file)
--- a/queue-5.10/series
+++ b/queue-5.10/series
@@ -159,4 +159,3 @@ btrfs-free-btrfs_path-before-copying-subvol-info-to-userspace.patch
 btrfs-sysfs-normalize-the-error-handling-branch-in-btrfs_init_sysfs.patch
 drm-amd-dc-dce120-fix-audio-register-mapping-stop-triggering-kasan.patch
 drm-amdgpu-always-register-an-mmu-notifier-for-userptr.patch
-drm-i915-fix-tlb-invalidation-for-gen12-video-and-compute-engines.patch

diff --git a/queue-5.4/drm-i915-fix-tlb-invalidation-for-gen12-video-and-compute-engines.patch b/queue-5.4/drm-i915-fix-tlb-invalidation-for-gen12-video-and-compute-engines.patch
deleted file mode 100644 (file)
index 714c7a0..0000000
--- a/queue-5.4/drm-i915-fix-tlb-invalidation-for-gen12-video-and-compute-engines.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 04aa64375f48a5d430b5550d9271f8428883e550 Mon Sep 17 00:00:00 2001
-From: Andrzej Hajda <andrzej.hajda@intel.com>
-Date: Mon, 14 Nov 2022 11:38:24 +0100
-Subject: drm/i915: fix TLB invalidation for Gen12 video and compute engines
-
-From: Andrzej Hajda <andrzej.hajda@intel.com>
-
-commit 04aa64375f48a5d430b5550d9271f8428883e550 upstream.
-
-In case of Gen12 video and compute engines, TLB_INV registers are masked -
-to modify one bit, corresponding bit in upper half of the register must
-be enabled, otherwise nothing happens.
-
-CVE: CVE-2022-4139
-Suggested-by: Chris Wilson <chris.p.wilson@intel.com>
-Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
-Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
-Cc: stable@vger.kernel.org
-Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/gpu/drm/i915/gt/intel_gt.c |    5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/drivers/gpu/drm/i915/gt/intel_gt.c
-+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
-@@ -348,6 +348,11 @@ void intel_gt_invalidate_tlbs(struct int
-               if (!i915_mmio_reg_offset(rb.reg))
-                       continue;
- 
-+              if (GRAPHICS_VER(i915) == 12 && (engine->class == VIDEO_DECODE_CLASS ||
-+                  engine->class == VIDEO_ENHANCEMENT_CLASS ||
-+                  engine->class == COMPUTE_CLASS))
-+                      rb.bit = _MASKED_BIT_ENABLE(rb.bit);
-+
-               intel_uncore_write_fw(uncore, rb.reg, rb.bit);
-       }
- 

diff --git a/queue-5.4/series b/queue-5.4/series
index 483b04d181b63b2a558d91442f816e4999e9668c..e5add3c490085e33373fa37883ad99f1fc7167ff 100644 (file)
--- a/queue-5.4/series
+++ b/queue-5.4/series
@@ -84,4 +84,3 @@ btrfs-free-btrfs_path-before-copying-subvol-info-to-userspace.patch
 btrfs-sysfs-normalize-the-error-handling-branch-in-btrfs_init_sysfs.patch
 drm-amd-dc-dce120-fix-audio-register-mapping-stop-triggering-kasan.patch
 drm-amdgpu-always-register-an-mmu-notifier-for-userptr.patch
-drm-i915-fix-tlb-invalidation-for-gen12-video-and-compute-engines.patch