clk: renesas: r9a08g046: Add RSPI clocks and resets

Add clock and reset definitions for the three RSPI (Serial Peripheral
Interface) channels on the RZ/G3L (R9A08G046) SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260505071544.8965-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a08g046-cpg.c
index fe3cb9a4f0eccae048e3b4d0d9e07235b3f619e9..fc9db5a2f0ac669babda403113c86e6cceabc9d4 100644 (file)
--- a/drivers/clk/renesas/r9a08g046-cpg.c
+++ b/drivers/clk/renesas/r9a08g046-cpg.c
@@ -19,9 +19,11 @@
 #define G3L_CPG_PL3_DDIV               (0x208)
 #define G3L_CPG_CA55CORE_DDIV          (0x234)
 #define G3L_CPG_RSCI_DDIV              (0x238)
+#define G3L_CPG_RSPI_DDIV              (0x23c)
 #define G3L_CLKDIVSTATUS               (0x280)
 #define G3L_CPG_ETH_SSEL               (0x410)
 #define G3L_CPG_RSCI_SSEL              (0x414)
+#define G3L_CPG_RSPI_SSEL              (0x418)
 #define G3L_CPG_ETH_SDIV               (0x434)
 
 /* RZ/G3L Specific division configuration.  */
@@ -36,6 +38,9 @@
 #define G3L_DIV_RSCI1          DDIV_PACK(G3L_CPG_RSCI_DDIV, 2, 2)
 #define G3L_DIV_RSCI2          DDIV_PACK(G3L_CPG_RSCI_DDIV, 4, 2)
 #define G3L_DIV_RSCI3          DDIV_PACK(G3L_CPG_RSCI_DDIV, 6, 2)
+#define G3L_DIV_RSPI0          DDIV_PACK(G3L_CPG_RSPI_DDIV, 0, 2)
+#define G3L_DIV_RSPI1          DDIV_PACK(G3L_CPG_RSPI_DDIV, 2, 2)
+#define G3L_DIV_RSPI2          DDIV_PACK(G3L_CPG_RSPI_DDIV, 4, 2)
 #define G3L_SDIV_ETH_A         DDIV_PACK(G3L_CPG_ETH_SDIV, 0, 2)
 #define G3L_SDIV_ETH_B         DDIV_PACK(G3L_CPG_ETH_SDIV, 4, 1)
 #define G3L_SDIV_ETH_C         DDIV_PACK(G3L_CPG_ETH_SDIV, 8, 2)
@@ -53,6 +58,9 @@
 #define G3L_DIV_RSCI1_STS      DDIV_PACK(G3L_CLKDIVSTATUS, 17, 1)
 #define G3L_DIV_RSCI2_STS      DDIV_PACK(G3L_CLKDIVSTATUS, 18, 1)
 #define G3L_DIV_RSCI3_STS      DDIV_PACK(G3L_CLKDIVSTATUS, 19, 1)
+#define G3L_DIV_RSPI0_STS      DDIV_PACK(G3L_CLKDIVSTATUS, 20, 1)
+#define G3L_DIV_RSPI1_STS      DDIV_PACK(G3L_CLKDIVSTATUS, 21, 1)
+#define G3L_DIV_RSPI2_STS      DDIV_PACK(G3L_CLKDIVSTATUS, 22, 1)
 
 /* RZ/G3L Specific clocks select. */
 #define G3L_SEL_ETH0_TX                SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 0, 1)
@@ -69,6 +77,9 @@
 #define G3L_SEL_RSCI1          SEL_PLL_PACK(G3L_CPG_RSCI_SSEL, 2, 2)
 #define G3L_SEL_RSCI2          SEL_PLL_PACK(G3L_CPG_RSCI_SSEL, 4, 2)
 #define G3L_SEL_RSCI3          SEL_PLL_PACK(G3L_CPG_RSCI_SSEL, 6, 2)
+#define G3L_SEL_RSPI0          SEL_PLL_PACK(G3L_CPG_RSPI_SSEL, 0, 2)
+#define G3L_SEL_RSPI1          SEL_PLL_PACK(G3L_CPG_RSPI_SSEL, 2, 2)
+#define G3L_SEL_RSPI2          SEL_PLL_PACK(G3L_CPG_RSPI_SSEL, 4, 2)
 
 /* PLL 1/4/6/7 configuration registers macro. */
 #define G3L_PLL1467_CONF(clk1, clk2, setting)  ((clk1) << 22 | (clk2) << 12 | (setting))
@@ -106,6 +117,9 @@ enum clk_ids {
        CLK_SEL_RSCI1,
        CLK_SEL_RSCI2,
        CLK_SEL_RSCI3,
+       CLK_SEL_RSPI0,
+       CLK_SEL_RSPI1,
+       CLK_SEL_RSPI2,
        CLK_ETH0_TR,
        CLK_ETH0_RM,
        CLK_ETH1_TR,
@@ -116,6 +130,14 @@ enum clk_ids {
 };
 
 /* Divider tables */
+static const struct clk_div_table dtable_1_8[] = {
+       { 0, 1 },
+       { 1, 2 },
+       { 2, 4 },
+       { 3, 8 },
+       { 0, 0 },
+};
+
 static const struct clk_div_table dtable_1_32[] = {
        { 0, 1 },
        { 1, 2 },
@@ -202,6 +224,9 @@ static const struct cpg_core_clk r9a08g046_core_clks[] __initconst = {
        DEF_MUX(".sel_rsci1", CLK_SEL_RSCI1, G3L_SEL_RSCI1, sel_rsci_rspi),
        DEF_MUX(".sel_rsci2", CLK_SEL_RSCI2, G3L_SEL_RSCI2, sel_rsci_rspi),
        DEF_MUX(".sel_rsci3", CLK_SEL_RSCI3, G3L_SEL_RSCI3, sel_rsci_rspi),
+       DEF_MUX(".sel_rspi0", CLK_SEL_RSPI0, G3L_SEL_RSPI0, sel_rsci_rspi),
+       DEF_MUX(".sel_rspi1", CLK_SEL_RSPI1, G3L_SEL_RSPI1, sel_rsci_rspi),
+       DEF_MUX(".sel_rspi2", CLK_SEL_RSPI2, G3L_SEL_RSPI2, sel_rsci_rspi),
        DEF_MUX(".sel_eth0_tx", CLK_SEL_ETH0_TX, G3L_SEL_ETH0_TX, sel_eth0_tx),
        DEF_MUX(".sel_eth0_rx", CLK_SEL_ETH0_RX, G3L_SEL_ETH0_RX, sel_eth0_rx),
        DEF_MUX(".sel_eth0_rm", CLK_SEL_ETH0_RM, G3L_SEL_ETH0_RM, sel_eth0_rm),
@@ -236,6 +261,12 @@ static const struct cpg_core_clk r9a08g046_core_clks[] __initconst = {
                    dtable_2_16, 0, 100000000UL, 0, NULL),
        DEF_G3S_DIV("P16", R9A08G046_CLK_P16, CLK_SEL_RSCI3, G3L_DIV_RSCI3, G3L_DIV_RSCI3_STS,
                    dtable_2_16, 0, 100000000UL, 0, NULL),
+       DEF_G3S_DIV("P17", R9A08G046_CLK_P17, CLK_SEL_RSPI0, G3L_DIV_RSPI0, G3L_DIV_RSPI0_STS,
+                   dtable_1_8, 0, 200000000UL, 0, NULL),
+       DEF_G3S_DIV("P18", R9A08G046_CLK_P18, CLK_SEL_RSPI1, G3L_DIV_RSPI1, G3L_DIV_RSPI1_STS,
+                   dtable_1_8, 0, 200000000UL, 0, NULL),
+       DEF_G3S_DIV("P19", R9A08G046_CLK_P19, CLK_SEL_RSPI2, G3L_DIV_RSPI2, G3L_DIV_RSPI2_STS,
+                   dtable_1_8, 0, 200000000UL, 0, NULL),
        DEF_FIXED("HP", R9A08G046_CLK_HP, CLK_PLL6_DIV10, 1, 1),
        DEF_MUX_FLAGS("ETHTX01", R9A08G046_CLK_ETHTX01, G3L_SEL_ETH0_CLK_TX_I, sel_eth0_clk_tx_i,
                      CLK_SET_RATE_PARENT),
@@ -345,6 +376,18 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
                                        MSTOP(BUS_MCPU2, BIT(5))),
        DEF_MOD("scif5_clk_pck",        R9A08G046_SCIF5_CLK_PCK, R9A08G046_CLK_P0, 0x584, 5,
                                        MSTOP(BUS_MCPU3, BIT(4))),
+       DEF_MOD("rspi0_pclk",           R9A08G046_RSPI0_PCLK, R9A08G046_CLK_P3, 0x590, 0,
+                                       MSTOP(BUS_MCPU1, BIT(14))),
+       DEF_MOD("rspi1_pclk",           R9A08G046_RSPI1_PCLK, R9A08G046_CLK_P3, 0x590, 1,
+                                       MSTOP(BUS_MCPU1, BIT(15))),
+       DEF_MOD("rspi2_pclk",           R9A08G046_RSPI2_PCLK, R9A08G046_CLK_P3, 0x590, 2,
+                                       MSTOP(BUS_MCPU2, BIT(0))),
+       DEF_MOD("rspi0_tclk",           R9A08G046_RSPI0_TCLK, R9A08G046_CLK_P17, 0x590, 8,
+                                       MSTOP(BUS_MCPU1, BIT(14))),
+       DEF_MOD("rspi1_tclk",           R9A08G046_RSPI1_TCLK, R9A08G046_CLK_P18, 0x590, 9,
+                                       MSTOP(BUS_MCPU1, BIT(15))),
+       DEF_MOD("rspi2_tclk",           R9A08G046_RSPI2_TCLK, R9A08G046_CLK_P19, 0x590, 10,
+                                       MSTOP(BUS_MCPU2, BIT(0))),
        DEF_MOD("gpio_hclk",            R9A08G046_GPIO_HCLK, R9A08G046_OSCCLK, 0x598, 0,
                                        MSTOP(BUS_PERI_CPU, BIT(6))),
        DEF_MOD("rsci0_pclk",           R9A08G046_RSCI0_PCLK, R9A08G046_CLK_P0, 0x618, 0,
@@ -388,6 +431,12 @@ static const struct rzg2l_reset r9a08g046_resets[] = {
        DEF_RST(R9A08G046_SCIF3_RST_SYSTEM_N, 0x884, 3),
        DEF_RST(R9A08G046_SCIF4_RST_SYSTEM_N, 0x884, 4),
        DEF_RST(R9A08G046_SCIF5_RST_SYSTEM_N, 0x884, 5),
+       DEF_RST(R9A08G046_RSPI0_PRESETN, 0x890, 0),
+       DEF_RST(R9A08G046_RSPI1_PRESETN, 0x890, 1),
+       DEF_RST(R9A08G046_RSPI2_PRESETN, 0x890, 2),
+       DEF_RST(R9A08G046_RSPI0_TRESETN, 0x890, 8),
+       DEF_RST(R9A08G046_RSPI1_TRESETN, 0x890, 9),
+       DEF_RST(R9A08G046_RSPI2_TRESETN, 0x890, 10),
        DEF_RST(R9A08G046_GPIO_RSTN, 0x898, 0),
        DEF_RST(R9A08G046_GPIO_PORT_RESETN, 0x898, 1),
        DEF_RST(R9A08G046_GPIO_SPARE_RESETN, 0x898, 2),