RISC-V: Fine tune vmadc/vmsbc RA constraint

gcc/ChangeLog:

	* config/riscv/vector.md: Refine vmadc/vmsbc RA constraint.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/narrow_constraint-13.c: New test.
	* gcc.target/riscv/rvv/base/narrow_constraint-14.c: New test.
	* gcc.target/riscv/rvv/base/narrow_constraint-15.c: New test.
	* gcc.target/riscv/rvv/base/narrow_constraint-16.c: New test.

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index eb8e0b44e58c7d27a6685ebb6868d9888cfdd8b9..b3d23441679297d4c3062df3624c20de6d04b7f2 100644 (file)
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -2450,15 +2450,15 @@
    (set (attr "avl_type") (symbol_ref "INTVAL (operands[7])"))])
 
 (define_insn "@pred_madc<mode>"
-  [(set (match_operand:<VM> 0 "register_operand"        "=&vr, &vr")
+  [(set (match_operand:<VM> 0 "register_operand"         "=vr, &vr, &vr")
        (unspec:<VM>
           [(plus:VI
-            (match_operand:VI 1 "register_operand"     "  vr,  vr")
-            (match_operand:VI 2 "vector_arith_operand" "  vr,  vi"))
-           (match_operand:<VM> 3 "register_operand"    "  vm,  vm")
+            (match_operand:VI 1 "register_operand"     "  %0,  vr,  vr")
+            (match_operand:VI 2 "vector_arith_operand" "vrvi,  vr,  vi"))
+           (match_operand:<VM> 3 "register_operand"    "  vm,  vm,  vm")
            (unspec:<VM>
-             [(match_operand 4 "vector_length_operand" "  rK,  rK")
-              (match_operand 5 "const_int_operand"     "   i,   i")
+             [(match_operand 4 "vector_length_operand" "  rK,  rK,  rK")
+              (match_operand 5 "const_int_operand"     "   i,   i,   i")
               (reg:SI VL_REGNUM)
               (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
   "TARGET_VECTOR"
@@ -2469,15 +2469,15 @@
    (set (attr "avl_type") (symbol_ref "INTVAL (operands[5])"))])
 
 (define_insn "@pred_msbc<mode>"
-  [(set (match_operand:<VM> 0 "register_operand"        "=&vr")
+  [(set (match_operand:<VM> 0 "register_operand"        "=vr, vr, &vr")
        (unspec:<VM>
           [(minus:VI
-            (match_operand:VI 1 "register_operand"     "  vr")
-            (match_operand:VI 2 "register_operand"     "  vr"))
-           (match_operand:<VM> 3 "register_operand"    "  vm")
+            (match_operand:VI 1 "register_operand"     "  0, vr,  vr")
+            (match_operand:VI 2 "register_operand"     " vr,  0,  vr"))
+           (match_operand:<VM> 3 "register_operand"    " vm, vm,  vm")
            (unspec:<VM>
-             [(match_operand 4 "vector_length_operand" "  rK")
-              (match_operand 5 "const_int_operand"     "   i")
+             [(match_operand 4 "vector_length_operand" " rK, rK,  rK")
+              (match_operand 5 "const_int_operand"     "  i,  i,   i")
               (reg:SI VL_REGNUM)
               (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
   "TARGET_VECTOR"
@@ -2488,16 +2488,16 @@
    (set (attr "avl_type") (symbol_ref "INTVAL (operands[5])"))])
 
 (define_insn "@pred_madc<mode>_scalar"
-  [(set (match_operand:<VM> 0 "register_operand"         "=&vr")
+  [(set (match_operand:<VM> 0 "register_operand"         "=vr, &vr")
        (unspec:<VM>
           [(plus:VI_QHS
             (vec_duplicate:VI_QHS
-              (match_operand:<VEL> 2 "register_operand" "   r"))
-            (match_operand:VI_QHS 1 "register_operand"  "  vr"))
-           (match_operand:<VM> 3 "register_operand"     "  vm")
+              (match_operand:<VEL> 2 "register_operand" "  r,   r"))
+            (match_operand:VI_QHS 1 "register_operand"  "  0,  vr"))
+           (match_operand:<VM> 3 "register_operand"     " vm,  vm")
            (unspec:<VM>
-             [(match_operand 4 "vector_length_operand"  "  rK")
-              (match_operand 5 "const_int_operand"      "   i")
+             [(match_operand 4 "vector_length_operand"  " rK,  rK")
+              (match_operand 5 "const_int_operand"      "  i,   i")
               (reg:SI VL_REGNUM)
               (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
   "TARGET_VECTOR"
@@ -2508,16 +2508,16 @@
    (set (attr "avl_type") (symbol_ref "INTVAL (operands[5])"))])
 
 (define_insn "@pred_msbc<mode>_scalar"
-  [(set (match_operand:<VM> 0 "register_operand"         "=&vr")
+  [(set (match_operand:<VM> 0 "register_operand"         "=vr, &vr")
        (unspec:<VM>
           [(minus:VI_QHS
             (vec_duplicate:VI_QHS
-              (match_operand:<VEL> 2 "reg_or_0_operand" "  rJ"))
-            (match_operand:VI_QHS 1 "register_operand"  "  vr"))
-           (match_operand:<VM> 3 "register_operand"     "  vm")
+              (match_operand:<VEL> 2 "reg_or_0_operand" " rJ,  rJ"))
+            (match_operand:VI_QHS 1 "register_operand"  "  0,  vr"))
+           (match_operand:<VM> 3 "register_operand"     " vm,  vm")
            (unspec:<VM>
-             [(match_operand 4 "vector_length_operand"  "  rK")
-              (match_operand 5 "const_int_operand"      "   i")
+             [(match_operand 4 "vector_length_operand"  " rK,  rK")
+              (match_operand 5 "const_int_operand"      "  i,   i")
               (reg:SI VL_REGNUM)
               (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
   "TARGET_VECTOR"
@@ -2557,16 +2557,16 @@
 })
 
 (define_insn "*pred_madc<mode>_scalar"
-  [(set (match_operand:<VM> 0 "register_operand"         "=&vr")
+  [(set (match_operand:<VM> 0 "register_operand"         "=vr, &vr")
        (unspec:<VM>
           [(plus:VI_D
             (vec_duplicate:VI_D
-              (match_operand:<VEL> 2 "reg_or_0_operand" "  rJ"))
-            (match_operand:VI_D 1 "register_operand"    "  vr"))
-           (match_operand:<VM> 3 "register_operand"     "  vm")
+              (match_operand:<VEL> 2 "reg_or_0_operand" " rJ,  rJ"))
+            (match_operand:VI_D 1 "register_operand"    "  0,  vr"))
+           (match_operand:<VM> 3 "register_operand"     " vm,  vm")
            (unspec:<VM>
-             [(match_operand 4 "vector_length_operand"  "  rK")
-              (match_operand 5 "const_int_operand"      "   i")
+             [(match_operand 4 "vector_length_operand"  " rK,  rK")
+              (match_operand 5 "const_int_operand"      "  i,   i")
               (reg:SI VL_REGNUM)
               (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
   "TARGET_VECTOR"
@@ -2577,17 +2577,17 @@
    (set (attr "avl_type") (symbol_ref "INTVAL (operands[5])"))])
 
 (define_insn "*pred_madc<mode>_extended_scalar"
-  [(set (match_operand:<VM> 0 "register_operand"             "=&vr")
+  [(set (match_operand:<VM> 0 "register_operand"             "=vr, &vr")
        (unspec:<VM>
           [(plus:VI_D
             (vec_duplicate:VI_D
               (sign_extend:<VEL>
-                (match_operand:<VSUBEL> 2 "reg_or_0_operand" "  rJ")))
-            (match_operand:VI_D 1 "register_operand"         "  vr"))
-           (match_operand:<VM> 3 "register_operand"          "  vm")
+                (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ,  rJ")))
+            (match_operand:VI_D 1 "register_operand"         "  0,  vr"))
+           (match_operand:<VM> 3 "register_operand"          " vm,  vm")
            (unspec:<VM>
-             [(match_operand 4 "vector_length_operand"       "  rK")
-              (match_operand 5 "const_int_operand"           "   i")
+             [(match_operand 4 "vector_length_operand"       " rK,  rK")
+              (match_operand 5 "const_int_operand"           "  i,   i")
               (reg:SI VL_REGNUM)
               (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
   "TARGET_VECTOR"
@@ -2627,16 +2627,16 @@
 })
 
 (define_insn "*pred_msbc<mode>_scalar"
-  [(set (match_operand:<VM> 0 "register_operand"         "=&vr")
+  [(set (match_operand:<VM> 0 "register_operand"         "=vr, &vr")
        (unspec:<VM>
           [(minus:VI_D
             (vec_duplicate:VI_D
-              (match_operand:<VEL> 2 "reg_or_0_operand" "  rJ"))
-            (match_operand:VI_D 1 "register_operand"    "  vr"))
-           (match_operand:<VM> 3 "register_operand"     "  vm")
+              (match_operand:<VEL> 2 "reg_or_0_operand" " rJ,  rJ"))
+            (match_operand:VI_D 1 "register_operand"    "  0,  vr"))
+           (match_operand:<VM> 3 "register_operand"     " vm,  vm")
            (unspec:<VM>
-             [(match_operand 4 "vector_length_operand"  "  rK")
-              (match_operand 5 "const_int_operand"      "   i")
+             [(match_operand 4 "vector_length_operand"  " rK,  rK")
+              (match_operand 5 "const_int_operand"      "  i,   i")
               (reg:SI VL_REGNUM)
               (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
   "TARGET_VECTOR"
@@ -2647,17 +2647,17 @@
    (set (attr "avl_type") (symbol_ref "INTVAL (operands[5])"))])
 
 (define_insn "*pred_msbc<mode>_extended_scalar"
-  [(set (match_operand:<VM> 0 "register_operand"             "=&vr")
+  [(set (match_operand:<VM> 0 "register_operand"              "=vr, &vr")
        (unspec:<VM>
           [(minus:VI_D
             (vec_duplicate:VI_D
               (sign_extend:<VEL>
-                (match_operand:<VSUBEL> 2 "reg_or_0_operand" "  rJ")))
-            (match_operand:VI_D 1 "register_operand"         "  vr"))
-           (match_operand:<VM> 3 "register_operand"          "  vm")
+                (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ,  rJ")))
+            (match_operand:VI_D 1 "register_operand"         "  0,  vr"))
+           (match_operand:<VM> 3 "register_operand"          " vm,  vm")
            (unspec:<VM>
-             [(match_operand 4 "vector_length_operand"       "  rK")
-              (match_operand 5 "const_int_operand"           "   i")
+             [(match_operand 4 "vector_length_operand"       " rK,  rK")
+              (match_operand 5 "const_int_operand"           "  i,   i")
               (reg:SI VL_REGNUM)
               (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
   "TARGET_VECTOR"
@@ -2668,14 +2668,14 @@
    (set (attr "avl_type") (symbol_ref "INTVAL (operands[5])"))])
 
 (define_insn "@pred_madc<mode>_overflow"
-  [(set (match_operand:<VM> 0 "register_operand"        "=&vr, &vr")
+  [(set (match_operand:<VM> 0 "register_operand"         "=vr, &vr, &vr")
        (unspec:<VM>
           [(plus:VI
-            (match_operand:VI 1 "register_operand"     "  vr,  vr")
-            (match_operand:VI 2 "vector_arith_operand" "  vr,  vi"))
+            (match_operand:VI 1 "register_operand"     "  %0,  vr,  vr")
+            (match_operand:VI 2 "vector_arith_operand" "vrvi,  vr,  vi"))
            (unspec:<VM>
-             [(match_operand 3 "vector_length_operand" "  rK,  rK")
-              (match_operand 4 "const_int_operand"     "   i,   i")
+             [(match_operand 3 "vector_length_operand" "  rK,  rK,  rK")
+              (match_operand 4 "const_int_operand"     "   i,   i,   i")
               (reg:SI VL_REGNUM)
               (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
   "TARGET_VECTOR"
@@ -2686,14 +2686,14 @@
    (set (attr "avl_type") (symbol_ref "INTVAL (operands[4])"))])
 
 (define_insn "@pred_msbc<mode>_overflow"
-  [(set (match_operand:<VM> 0 "register_operand"        "=&vr")
+  [(set (match_operand:<VM> 0 "register_operand"         "=vr, vr, &vr, &vr")
        (unspec:<VM>
           [(minus:VI
-            (match_operand:VI 1 "register_operand"     "  vr")
-            (match_operand:VI 2 "register_operand"     "  vr"))
+            (match_operand:VI 1 "register_operand"     "   0,  vr,  vr,  vr")
+            (match_operand:VI 2 "register_operand"     "  vr,   0,  vr,  vi"))
            (unspec:<VM>
-             [(match_operand 3 "vector_length_operand" "  rK")
-              (match_operand 4 "const_int_operand"     "   i")
+             [(match_operand 3 "vector_length_operand" "  rK,  rK,  rK,  rK")
+              (match_operand 4 "const_int_operand"     "   i,   i,   i,   i")
               (reg:SI VL_REGNUM)
               (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
   "TARGET_VECTOR"
@@ -2704,15 +2704,15 @@
    (set (attr "avl_type") (symbol_ref "INTVAL (operands[4])"))])
 
 (define_insn "@pred_madc<mode>_overflow_scalar"
-  [(set (match_operand:<VM> 0 "register_operand"         "=&vr")
+  [(set (match_operand:<VM> 0 "register_operand"         "=vr, &vr")
        (unspec:<VM>
           [(plus:VI_QHS
             (vec_duplicate:VI_QHS
-              (match_operand:<VEL> 2 "reg_or_0_operand" "  rJ"))
-            (match_operand:VI_QHS 1 "register_operand"  "  vr"))
+              (match_operand:<VEL> 2 "reg_or_0_operand" " rJ,  rJ"))
+            (match_operand:VI_QHS 1 "register_operand"  "  0,  vr"))
            (unspec:<VM>
-             [(match_operand 3 "vector_length_operand"  "  rK")
-              (match_operand 4 "const_int_operand"      "   i")
+             [(match_operand 3 "vector_length_operand"  " rK,  rK")
+              (match_operand 4 "const_int_operand"      "  i,   i")
               (reg:SI VL_REGNUM)
               (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
   "TARGET_VECTOR"
@@ -2723,15 +2723,15 @@
    (set (attr "avl_type") (symbol_ref "INTVAL (operands[4])"))])
 
 (define_insn "@pred_msbc<mode>_overflow_scalar"
-  [(set (match_operand:<VM> 0 "register_operand"         "=&vr")
+  [(set (match_operand:<VM> 0 "register_operand"         "=vr, &vr")
        (unspec:<VM>
           [(minus:VI_QHS
             (vec_duplicate:VI_QHS
-              (match_operand:<VEL> 2 "reg_or_0_operand" "  rJ"))
-            (match_operand:VI_QHS 1 "register_operand"  "  vr"))
+              (match_operand:<VEL> 2 "reg_or_0_operand" " rJ,  rJ"))
+            (match_operand:VI_QHS 1 "register_operand"  "  0,  vr"))
            (unspec:<VM>
-             [(match_operand 3 "vector_length_operand"  "  rK")
-              (match_operand 4 "const_int_operand"      "   i")
+             [(match_operand 3 "vector_length_operand"  " rK,  rK")
+              (match_operand 4 "const_int_operand"      "  i,   i")
               (reg:SI VL_REGNUM)
               (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
   "TARGET_VECTOR"
@@ -2770,15 +2770,15 @@
 })
 
 (define_insn "*pred_madc<mode>_overflow_scalar"
-  [(set (match_operand:<VM> 0 "register_operand"         "=&vr")
+  [(set (match_operand:<VM> 0 "register_operand"         "=vr, &vr")
        (unspec:<VM>
           [(plus:VI_D
             (vec_duplicate:VI_D
-              (match_operand:<VEL> 2 "reg_or_0_operand" "  rJ"))
-            (match_operand:VI_D 1 "register_operand"    "  vr"))
+              (match_operand:<VEL> 2 "reg_or_0_operand" " rJ,  rJ"))
+            (match_operand:VI_D 1 "register_operand"    "  0,  vr"))
            (unspec:<VM>
-             [(match_operand 3 "vector_length_operand"  "  rK")
-              (match_operand 4 "const_int_operand"      "   i")
+             [(match_operand 3 "vector_length_operand"  " rK,  rK")
+              (match_operand 4 "const_int_operand"      "  i,   i")
               (reg:SI VL_REGNUM)
               (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
   "TARGET_VECTOR"
@@ -2789,16 +2789,16 @@
    (set (attr "avl_type") (symbol_ref "INTVAL (operands[4])"))])
 
 (define_insn "*pred_madc<mode>_overflow_extended_scalar"
-  [(set (match_operand:<VM> 0 "register_operand"             "=&vr")
+  [(set (match_operand:<VM> 0 "register_operand"             "=vr, &vr")
        (unspec:<VM>
           [(plus:VI_D
             (vec_duplicate:VI_D
               (sign_extend:<VEL>
-                (match_operand:<VSUBEL> 2 "reg_or_0_operand" "  rJ")))
-            (match_operand:VI_D 1 "register_operand"         "  vr"))
+                (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ,  rJ")))
+            (match_operand:VI_D 1 "register_operand"         "  0,  vr"))
            (unspec:<VM>
-             [(match_operand 3 "vector_length_operand"       "  rK")
-              (match_operand 4 "const_int_operand"           "   i")
+             [(match_operand 3 "vector_length_operand"       " rK,  rK")
+              (match_operand 4 "const_int_operand"           "  i,   i")
               (reg:SI VL_REGNUM)
               (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
   "TARGET_VECTOR"
@@ -2837,15 +2837,15 @@
 })
 
 (define_insn "*pred_msbc<mode>_overflow_scalar"
-  [(set (match_operand:<VM> 0 "register_operand"         "=&vr")
+  [(set (match_operand:<VM> 0 "register_operand"         "=vr, &vr")
        (unspec:<VM>
           [(minus:VI_D
             (vec_duplicate:VI_D
-              (match_operand:<VEL> 2 "reg_or_0_operand" "  rJ"))
-            (match_operand:VI_D 1 "register_operand"    "  vr"))
+              (match_operand:<VEL> 2 "reg_or_0_operand" " rJ,  rJ"))
+            (match_operand:VI_D 1 "register_operand"    "  0,  vr"))
            (unspec:<VM>
-             [(match_operand 3 "vector_length_operand"  "  rK")
-              (match_operand 4 "const_int_operand"      "   i")
+             [(match_operand 3 "vector_length_operand"  " rK,  rK")
+              (match_operand 4 "const_int_operand"      "  i,   i")
               (reg:SI VL_REGNUM)
               (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
   "TARGET_VECTOR"
@@ -2856,16 +2856,16 @@
    (set (attr "avl_type") (symbol_ref "INTVAL (operands[4])"))])
 
 (define_insn "*pred_msbc<mode>_overflow_extended_scalar"
-  [(set (match_operand:<VM> 0 "register_operand"             "=&vr")
+  [(set (match_operand:<VM> 0 "register_operand"             "=vr, &vr")
        (unspec:<VM>
           [(minus:VI_D
             (vec_duplicate:VI_D
               (sign_extend:<VEL>
-                (match_operand:<VSUBEL> 2 "reg_or_0_operand" "  rJ")))
-            (match_operand:VI_D 1 "register_operand"         "  vr"))
+                (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ,  rJ")))
+            (match_operand:VI_D 1 "register_operand"         "  0,  vr"))
            (unspec:<VM>
-             [(match_operand 3 "vector_length_operand"       "  rK")
-              (match_operand 4 "const_int_operand"           "   i")
+             [(match_operand 3 "vector_length_operand"      " rK,  rK")
+              (match_operand 4 "const_int_operand"          "  i,   i")
               (reg:SI VL_REGNUM)
               (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
   "TARGET_VECTOR"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-13.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-13.c
new file mode 100644 (file)
index 0000000..521af15
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-13.c
@@ -0,0 +1,133 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+
+#include "riscv_vector.h"
+
+void f0 (int16_t *base,int8_t *out,size_t vl)
+{
+    vint16m2_t v0 = __riscv_vle16_v_i16m2 (base, vl);
+    vint16m2_t v1 = __riscv_vle16_v_i16m2 ((int16_t *)(base + 100), vl);
+    vbool8_t m = __riscv_vlm_v_b8 ((uint8_t *)(base + 200), vl);
+    asm volatile("#" ::
+                : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27");
+
+    m = __riscv_vmadc_vvm_i16m2_b8 (v0, v1, m, 4);
+    asm volatile("#" ::
+                : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v29", "v30", "v31");
+
+    __riscv_vsm_v_b8 (out,m,vl);
+}
+
+void f1 (int16_t *base,int8_t *out,size_t vl)
+{
+    vint16m2_t v0 = __riscv_vle16_v_i16m2 (base, vl);
+    vint16m2_t v1 = __riscv_vle16_v_i16m2 ((int16_t *)(base + 100), vl);
+    vbool8_t m = __riscv_vlm_v_b8 ((uint8_t *)(base + 200), vl);
+    asm volatile("#" ::
+                : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27");
+
+    m = __riscv_vmadc_vvm_i16m2_b8 (v0, v1, m, 4);
+    asm volatile("#" ::
+                : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29", "v31");
+
+    __riscv_vsm_v_b8 (out,m,vl);
+}
+
+void f2 (int16_t *base,int8_t *out,size_t vl)
+{
+    vint16m2_t v0 = __riscv_vle16_v_i16m2 (base, vl);
+    vint16m2_t v1 = __riscv_vle16_v_i16m2 ((int16_t *)(base + 100), vl);
+    vbool8_t m = __riscv_vlm_v_b8 ((uint8_t *)(base + 200), vl);
+    asm volatile("#" ::
+                : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27");
+
+    m = __riscv_vmadc_vvm_i16m2_b8 (v0, v1, m, 4);
+    asm volatile("#" ::
+                : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29", "v30", "v31");
+
+    __riscv_vsm_v_b8 (out,m,vl);
+}
+
+void f3 (int16_t *base,int8_t *out,size_t vl)
+{
+    vint16mf2_t v0 = __riscv_vle16_v_i16mf2 (base, vl);
+    vint16mf2_t v1 = __riscv_vle16_v_i16mf2 ((int16_t *)(base + 100), vl);
+    vbool32_t m = __riscv_vlm_v_b32 ((uint8_t *)(base + 200), vl);
+    asm volatile("#" ::
+                : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29");
+
+    m = __riscv_vmadc_vvm_i16mf2_b32 (v0, v1, m, 4);
+    asm volatile("#" ::
+                : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29", "v30");
+
+    __riscv_vsm_v_b32 (out,m,vl);
+}
+
+void f4 (int16_t *base,int8_t *out,size_t vl)
+{
+    vint16mf2_t v0 = __riscv_vle16_v_i16mf2 (base, vl);
+    vint16mf2_t v1 = __riscv_vle16_v_i16mf2 ((int16_t *)(base + 100), vl);
+    vbool32_t m = __riscv_vlm_v_b32 ((uint8_t *)(base + 200), vl);
+    asm volatile("#" ::
+                : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29");
+
+    m = __riscv_vmadc_vvm_i16mf2_b32 (v0, v1, m, 4);
+    asm volatile("#" ::
+                : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29", "v31");
+
+    __riscv_vsm_v_b32 (out,m,vl);
+}
+
+void f5 (int16_t *base,int8_t *out,size_t vl)
+{
+    vint16mf2_t v0 = __riscv_vle16_v_i16mf2 (base, vl);
+    vint16mf2_t v1 = __riscv_vle16_v_i16mf2 ((int16_t *)(base + 100), vl);
+    vbool32_t m = __riscv_vlm_v_b32 ((uint8_t *)(base + 200), vl);
+    asm volatile("#" ::
+                : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29");
+
+    m = __riscv_vmadc_vvm_i16mf2_b32 (v0, v1, m, 4);
+    asm volatile("#" ::
+                : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v30", "v31");
+
+    __riscv_vsm_v_b32 (out,m,vl);
+}
+
+/* { dg-final { scan-assembler-not {vmv} } } */
+/* { dg-final { scan-assembler-not {csrr} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-14.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-14.c
new file mode 100644 (file)
index 0000000..66a8791
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-14.c
@@ -0,0 +1,133 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+
+#include "riscv_vector.h"
+
+void f0 (int16_t *base,int8_t *out,size_t vl)
+{
+    vint16m2_t v0 = __riscv_vle16_v_i16m2 (base, vl);
+    vint16m2_t v1 = __riscv_vle16_v_i16m2 ((int16_t *)(base + 100), vl);
+    vbool8_t m = __riscv_vlm_v_b8 ((uint8_t *)(base + 200), vl);
+    asm volatile("#" ::
+                : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27");
+
+    m = __riscv_vmsbc_vvm_i16m2_b8 (v0, v1, m, 4);
+    asm volatile("#" ::
+                : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v29", "v30", "v31");
+
+    __riscv_vsm_v_b8 (out,m,vl);
+}
+
+void f1 (int16_t *base,int8_t *out,size_t vl)
+{
+    vint16m2_t v0 = __riscv_vle16_v_i16m2 (base, vl);
+    vint16m2_t v1 = __riscv_vle16_v_i16m2 ((int16_t *)(base + 100), vl);
+    vbool8_t m = __riscv_vlm_v_b8 ((uint8_t *)(base + 200), vl);
+    asm volatile("#" ::
+                : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27");
+
+    m = __riscv_vmsbc_vvm_i16m2_b8 (v0, v1, m, 4);
+    asm volatile("#" ::
+                : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29", "v31");
+
+    __riscv_vsm_v_b8 (out,m,vl);
+}
+
+void f2 (int16_t *base,int8_t *out,size_t vl)
+{
+    vint16m2_t v0 = __riscv_vle16_v_i16m2 (base, vl);
+    vint16m2_t v1 = __riscv_vle16_v_i16m2 ((int16_t *)(base + 100), vl);
+    vbool8_t m = __riscv_vlm_v_b8 ((uint8_t *)(base + 200), vl);
+    asm volatile("#" ::
+                : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27");
+
+    m = __riscv_vmsbc_vvm_i16m2_b8 (v0, v1, m, 4);
+    asm volatile("#" ::
+                : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29", "v30", "v31");
+
+    __riscv_vsm_v_b8 (out,m,vl);
+}
+
+void f3 (int16_t *base,int8_t *out,size_t vl)
+{
+    vint16mf2_t v0 = __riscv_vle16_v_i16mf2 (base, vl);
+    vint16mf2_t v1 = __riscv_vle16_v_i16mf2 ((int16_t *)(base + 100), vl);
+    vbool32_t m = __riscv_vlm_v_b32 ((uint8_t *)(base + 200), vl);
+    asm volatile("#" ::
+                : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29");
+
+    m = __riscv_vmsbc_vvm_i16mf2_b32 (v0, v1, m, 4);
+    asm volatile("#" ::
+                : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29", "v30");
+
+    __riscv_vsm_v_b32 (out,m,vl);
+}
+
+void f4 (int16_t *base,int8_t *out,size_t vl)
+{
+    vint16mf2_t v0 = __riscv_vle16_v_i16mf2 (base, vl);
+    vint16mf2_t v1 = __riscv_vle16_v_i16mf2 ((int16_t *)(base + 100), vl);
+    vbool32_t m = __riscv_vlm_v_b32 ((uint8_t *)(base + 200), vl);
+    asm volatile("#" ::
+                : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29");
+
+    m = __riscv_vmsbc_vvm_i16mf2_b32 (v0, v1, m, 4);
+    asm volatile("#" ::
+                : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29", "v31");
+
+    __riscv_vsm_v_b32 (out,m,vl);
+}
+
+void f5 (int16_t *base,int8_t *out,size_t vl)
+{
+    vint16mf2_t v0 = __riscv_vle16_v_i16mf2 (base, vl);
+    vint16mf2_t v1 = __riscv_vle16_v_i16mf2 ((int16_t *)(base + 100), vl);
+    vbool32_t m = __riscv_vlm_v_b32 ((uint8_t *)(base + 200), vl);
+    asm volatile("#" ::
+                : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29");
+
+    m = __riscv_vmsbc_vvm_i16mf2_b32 (v0, v1, m, 4);
+    asm volatile("#" ::
+                : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v30", "v31");
+
+    __riscv_vsm_v_b32 (out,m,vl);
+}
+
+/* { dg-final { scan-assembler-not {vmv} } } */
+/* { dg-final { scan-assembler-not {csrr} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-15.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-15.c
new file mode 100644 (file)
index 0000000..b3add7b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-15.c
@@ -0,0 +1,127 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+
+#include "riscv_vector.h"
+
+void f0 (int16_t *base,int8_t *out,size_t vl)
+{
+    vint16m2_t v0 = __riscv_vle16_v_i16m2 (base, vl);
+    vint16m2_t v1 = __riscv_vle16_v_i16m2 ((int16_t *)(base + 100), vl);
+    asm volatile("#" ::
+                : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27");
+
+    vbool8_t m = __riscv_vmadc_vv_i16m2_b8 (v0, v1,4);
+    asm volatile("#" ::
+                : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v29", "v30", "v31");
+
+    __riscv_vsm_v_b8 (out,m,vl);
+}
+
+void f1 (int16_t *base,int8_t *out,size_t vl)
+{
+    vint16m2_t v0 = __riscv_vle16_v_i16m2 (base, vl);
+    vint16m2_t v1 = __riscv_vle16_v_i16m2 ((int16_t *)(base + 100), vl);
+    asm volatile("#" ::
+                : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27");
+
+    vbool8_t m = __riscv_vmadc_vv_i16m2_b8 (v0, v1,4);
+    asm volatile("#" ::
+                : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29", "v31");
+
+    __riscv_vsm_v_b8 (out,m,vl);
+}
+
+void f2 (int16_t *base,int8_t *out,size_t vl)
+{
+    vint16m2_t v0 = __riscv_vle16_v_i16m2 (base, vl);
+    vint16m2_t v1 = __riscv_vle16_v_i16m2 ((int16_t *)(base + 100), vl);
+    asm volatile("#" ::
+                : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27");
+
+    vbool8_t m = __riscv_vmadc_vv_i16m2_b8 (v0, v1,4);
+    asm volatile("#" ::
+                : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29", "v30", "v31");
+
+    __riscv_vsm_v_b8 (out,m,vl);
+}
+
+void f3 (int16_t *base,int8_t *out,size_t vl)
+{
+    vint16mf2_t v0 = __riscv_vle16_v_i16mf2 (base, vl);
+    vint16mf2_t v1 = __riscv_vle16_v_i16mf2 ((int16_t *)(base + 100), vl);
+    asm volatile("#" ::
+                : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29");
+
+    vbool32_t m = __riscv_vmadc_vv_i16mf2_b32 (v0, v1,4);
+    asm volatile("#" ::
+                : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29", "v30");
+
+    __riscv_vsm_v_b32 (out,m,vl);
+}
+
+void f4 (int16_t *base,int8_t *out,size_t vl)
+{
+    vint16mf2_t v0 = __riscv_vle16_v_i16mf2 (base, vl);
+    vint16mf2_t v1 = __riscv_vle16_v_i16mf2 ((int16_t *)(base + 100), vl);
+    asm volatile("#" ::
+                : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29");
+
+    vbool32_t m = __riscv_vmadc_vv_i16mf2_b32 (v0, v1,4);
+    asm volatile("#" ::
+                : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29", "v31");
+
+    __riscv_vsm_v_b32 (out,m,vl);
+}
+
+void f5 (int16_t *base,int8_t *out,size_t vl)
+{
+    vint16mf2_t v0 = __riscv_vle16_v_i16mf2 (base, vl);
+    vint16mf2_t v1 = __riscv_vle16_v_i16mf2 ((int16_t *)(base + 100), vl);
+    asm volatile("#" ::
+                : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29");
+
+    vbool32_t m = __riscv_vmadc_vv_i16mf2_b32 (v0, v1,4);
+    asm volatile("#" ::
+                : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v30", "v31");
+
+    __riscv_vsm_v_b32 (out,m,vl);
+}
+
+/* { dg-final { scan-assembler-not {vmv} } } */
+/* { dg-final { scan-assembler-not {csrr} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-16.c
new file mode 100644 (file)
index 0000000..468471c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/narrow_constraint-16.c
@@ -0,0 +1,127 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+
+#include "riscv_vector.h"
+
+void f0 (int16_t *base,int8_t *out,size_t vl)
+{
+    vint16m2_t v0 = __riscv_vle16_v_i16m2 (base, vl);
+    vint16m2_t v1 = __riscv_vle16_v_i16m2 ((int16_t *)(base + 100), vl);
+    asm volatile("#" ::
+                : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27");
+
+    vbool8_t m = __riscv_vmsbc_vv_i16m2_b8 (v0, v1,4);
+    asm volatile("#" ::
+                : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v29", "v30", "v31");
+
+    __riscv_vsm_v_b8 (out,m,vl);
+}
+
+void f1 (int16_t *base,int8_t *out,size_t vl)
+{
+    vint16m2_t v0 = __riscv_vle16_v_i16m2 (base, vl);
+    vint16m2_t v1 = __riscv_vle16_v_i16m2 ((int16_t *)(base + 100), vl);
+    asm volatile("#" ::
+                : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27");
+
+    vbool8_t m = __riscv_vmsbc_vv_i16m2_b8 (v0, v1,4);
+    asm volatile("#" ::
+                : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29", "v31");
+
+    __riscv_vsm_v_b8 (out,m,vl);
+}
+
+void f2 (int16_t *base,int8_t *out,size_t vl)
+{
+    vint16m2_t v0 = __riscv_vle16_v_i16m2 (base, vl);
+    vint16m2_t v1 = __riscv_vle16_v_i16m2 ((int16_t *)(base + 100), vl);
+    asm volatile("#" ::
+                : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27");
+
+    vbool8_t m = __riscv_vmsbc_vv_i16m2_b8 (v0, v1,4);
+    asm volatile("#" ::
+                : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29", "v30", "v31");
+
+    __riscv_vsm_v_b8 (out,m,vl);
+}
+
+void f3 (int16_t *base,int8_t *out,size_t vl)
+{
+    vint16mf2_t v0 = __riscv_vle16_v_i16mf2 (base, vl);
+    vint16mf2_t v1 = __riscv_vle16_v_i16mf2 ((int16_t *)(base + 100), vl);
+    asm volatile("#" ::
+                : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29");
+
+    vbool32_t m = __riscv_vmsbc_vv_i16mf2_b32 (v0, v1,4);
+    asm volatile("#" ::
+                : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29", "v30");
+
+    __riscv_vsm_v_b32 (out,m,vl);
+}
+
+void f4 (int16_t *base,int8_t *out,size_t vl)
+{
+    vint16mf2_t v0 = __riscv_vle16_v_i16mf2 (base, vl);
+    vint16mf2_t v1 = __riscv_vle16_v_i16mf2 ((int16_t *)(base + 100), vl);
+    asm volatile("#" ::
+                : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29");
+
+    vbool32_t m = __riscv_vmsbc_vv_i16mf2_b32 (v0, v1,4);
+    asm volatile("#" ::
+                : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29", "v31");
+
+    __riscv_vsm_v_b32 (out,m,vl);
+}
+
+void f5 (int16_t *base,int8_t *out,size_t vl)
+{
+    vint16mf2_t v0 = __riscv_vle16_v_i16mf2 (base, vl);
+    vint16mf2_t v1 = __riscv_vle16_v_i16mf2 ((int16_t *)(base + 100), vl);
+    asm volatile("#" ::
+                : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v29");
+
+    vbool32_t m = __riscv_vmsbc_vv_i16mf2_b32 (v0, v1,4);
+    asm volatile("#" ::
+                : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
+                  "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
+                  "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
+                  "v26", "v27", "v28", "v30", "v31");
+
+    __riscv_vsm_v_b32 (out,m,vl);
+}
+
+/* { dg-final { scan-assembler-not {vmv} } } */
+/* { dg-final { scan-assembler-not {csrr} } } */