ASoC: SOF: amd: fix for ipc flags check

Firmware will set dsp_ack to 1 when firmware sends response for the IPC
command issued by host. Similarly dsp_msg flag will be updated to 1.

During ACP D0 entry, the value read from the sof_dsp_ack_write scratch
flag can be uninitialized. A non-zero garbage value is treated as a
pending DSP IPC ack before SOF_FW_BOOT_COMPLETE, causing a spurious
"IPC reply before FW_BOOT_COMPLETE" log.

Fix the condition checks for ipc flags.

Fixes: 738a2b5e2cc9 ("ASoC: SOF: amd: Add IPC support for ACP IP block")
Link: https://github.com/thesofproject/linux/pull/5642
Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Tested-by: Umang Jain <uajain@igalia.com>
Link: https://patch.msgid.link/20260609160938.3717513-1-Vijendar.Mukunda@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/sound/soc/sof/amd/acp-ipc.c b/sound/soc/sof/amd/acp-ipc.c
index 3cd4674dd80075c830da0015fce49c761f40b29d..94025bc799ea4083efaac2f903d916b1f079f66a 100644 (file)
--- a/sound/soc/sof/amd/acp-ipc.c
+++ b/sound/soc/sof/amd/acp-ipc.c
@@ -181,14 +181,14 @@ irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context)
        }
 
        dsp_msg = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_msg_write);
-       if (dsp_msg) {
+       if (dsp_msg == ACP_DSP_MSG_SET) {
                snd_sof_ipc_msgs_rx(sdev);
                acp_dsp_ipc_host_done(sdev);
                ipc_irq = true;
        }
 
        dsp_ack = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SCRATCH_REG_0 + dsp_ack_write);
-       if (dsp_ack) {
+       if (dsp_ack == ACP_DSP_ACK_SET) {
                if (likely(sdev->fw_state == SOF_FW_BOOT_COMPLETE)) {
                        guard(spinlock_irq)(&sdev->ipc_lock);
 

diff --git a/sound/soc/sof/amd/acp.h b/sound/soc/sof/amd/acp.h
index 2b7ea8c6410602b4277477d73b158706b6b6b5a2..7bcb76676a984a1aaaf3a94f876ea65bcabab115 100644 (file)
--- a/sound/soc/sof/amd/acp.h
+++ b/sound/soc/sof/amd/acp.h
@@ -116,6 +116,8 @@
 #define ACP_SRAM_PAGE_COUNT                    128
 #define ACP6X_SDW_MAX_MANAGER_COUNT            2
 #define ACP70_SDW_MAX_MANAGER_COUNT            ACP6X_SDW_MAX_MANAGER_COUNT
+#define ACP_DSP_MSG_SET                                1
+#define ACP_DSP_ACK_SET                                1
 
 enum clock_source {
        ACP_CLOCK_96M = 0,