+2023-12-04 Andrew Pinski <quic_apinski@quicinc.com>
+
+ * match.pd (zero_one_valued_p): For convert
+ make sure type is not a signed 1-bit integer.
+
+2023-12-04 Jeff Law <jlaw@ventanamicro.com>
+
+ * config/microblaze/microblaze.md (movhi): Use %i for half-word
+ loads to properly select between lhu/lhui.
+
+2023-12-04 Robin Dapp <rdapp@ventanamicro.com>
+
+ * config/riscv/riscv-string.cc (expand_rawmemchr): Increment
+ source address by vl * element_size.
+
+2023-12-04 Robin Dapp <rdapp@ventanamicro.com>
+
+ * config/riscv/riscv-opts.h (enum riscv_stringop_strategy_enum):
+ Rename...
+ (enum stringop_strategy_enum): ... to this.
+ * config/riscv/riscv-string.cc (riscv_expand_block_move): New
+ wrapper expander handling the strategies and delegation.
+ (riscv_expand_block_move_scalar): Rename function and make
+ static.
+ (expand_block_move): Remove strategy handling.
+ * config/riscv/riscv.md: Call expander wrapper.
+ * config/riscv/riscv.opt: Rename.
+
+2023-12-04 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/112785
+ * function.h (get_new_clique): New inline function handling
+ last_clique overflow.
+ * cfgrtl.cc (duplicate_insn_chain): Use it.
+ * tree-cfg.cc (gimple_duplicate_bb): Likewise.
+ * tree-inline.cc (remap_dependence_clique): Likewise.
+
+2023-12-04 Christoph Müllner <christoph.muellner@vrull.eu>
+
+ PR target/112650
+ * doc/invoke.texi: Document riscv-strcmp-inline-limit.
+
+2023-12-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
+
+ PR target/112431
+ * config/riscv/vector.md: Fix incorrect overlap in v0.
+
+2023-12-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
+
+ PR target/112431
+ * config/riscv/vector.md: Add highest-number overlap support.
+
+2023-12-04 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/112818
+ * tree-vect-stmts.cc (vectorizable_bswap): Check input and
+ output vector types have the same size.
+
+2023-12-04 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/112827
+ * tree-scalar-evolution.cc (final_value_replacement_loop):
+ Do not release SSA name but keep a dead initialization around.
+
+2023-12-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
+
+ PR target/112431
+ * config/riscv/vector.md: Remove earlyclobber from widen reduction.
+
+2023-12-04 Indu Bhagat <indu.bhagat@oracle.com>
+
+ PR debug/112656
+ * btfout.cc (btf_asm_type): Fixup ctti_name for all
+ BTF types of kind BTF_KIND_FUNC_PROTO.
+
+2023-12-04 Indu Bhagat <indu.bhagat@oracle.com>
+
+ PR debug/112768
+ * btfout.cc (get_btf_type_name): New definition.
+ (btf_collect_datasec): Update dtd_name to the original type name
+ string.
+ (btf_asm_type_ref): Use the new get_btf_type_name function
+ instead.
+ (btf_asm_type): Likewise.
+ (btf_asm_func_type): Likewise.
+
+2023-12-04 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/112837
+ * config/i386/i386.cc (ix86_elim_entry_set_got): Before checking
+ for UNSPEC_SET_GOT check that SET_SRC is UNSPEC. Use SET_SRC and
+ SET_DEST macros instead of XEXP, rename vec variable to set.
+
+2023-12-04 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/112816
+ * config/i386/sse.md (signbit<mode>2): Force operands[1] into a REG.
+
+2023-12-04 Feng Wang <wangfeng@eswincomputing.com>
+
+ * common/config/riscv/riscv-common.cc: Add zvkb ISA info.
+ * config/riscv/riscv.opt: Add Mask(ZVKB)
+
+2023-12-04 Fei Gao <gaofei@eswincomputing.com>
+ Xiao Zeng <zengxiao@eswincomputing.com>
+
+ * config/riscv/riscv.md (*mov<GPR:mode><X:mode>cc):move to sfb.md
+ * config/riscv/sfb.md: New file.
+
+2023-12-04 Kito Cheng <kito.cheng@sifive.com>
+
+ * config/riscv/riscv-cores.def: Add sifive-x280.
+ * doc/invoke.texi (RISC-V Options): Add sifive-x280
+
+2023-12-04 Kito Cheng <kito.cheng@sifive.com>
+
+ * common/config/riscv/riscv-common.cc (riscv_implied_predicator_t): New.
+ (riscv_implied_info_t::riscv_implied_info_t): New.
+ (riscv_implied_info_t::match): New.
+ (riscv_implied_info): New entry for zcf.
+ (riscv_subset_list::handle_implied_ext): Use
+ riscv_implied_info_t::match.
+ (riscv_subset_list::check_implied_ext): Ditto.
+ (riscv_subset_list::handle_combine_ext): Ditto.
+ (riscv_subset_list::parse): Move zcf implication handling to
+ riscv_implied_infos.
+
+2023-12-04 Kito Cheng <kito.cheng@sifive.com>
+
+ * common/config/riscv/riscv-common.cc
+ (riscv_subset_list::check_conflict_ext): New.
+ (riscv_subset_list::parse): Move checking conflict ext. to
+ check_conflict_ext.
+ * config/riscv/riscv-subset.h:
+ Add riscv_subset_list::check_conflict_ext.
+
+2023-12-04 Hu, Lin1 <lin1.hu@intel.com>
+
+ * common/config/i386/cpuinfo.h (get_available_features): Move USER_MSR
+ to the correct location.
+
+2023-12-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
+
+ * config/riscv/riscv.md: Rostify the constraints.
+
+2023-12-04 chenxiaolong <chenxiaolong@loongson.cn>
+
+ * doc/extend.texi: Add information about the intrinsic function of the vector
+ instruction.
+
2023-12-03 Jakub Jelinek <jakub@redhat.com>
PR middle-end/112807
+2023-12-04 Jason Merrill <jason@redhat.com>
+
+ * constexpr.cc (potential_constant_expression_1): Fix
+ check for loading volatile lvalue.
+
+2023-12-04 Jakub Jelinek <jakub@redhat.com>
+
+ PR c++/112795
+ * cp-tree.h (cp_convert_range_for): Change UNROLL type from
+ unsigned short to tree.
+ (finish_while_stmt_cond, finish_do_stmt, finish_for_cond): Likewise.
+ * parser.cc (cp_parser_statement): Pass NULL_TREE rather than 0 to
+ cp_parser_iteration_statement UNROLL argument.
+ (cp_parser_for, cp_parser_c_for): Change UNROLL type from
+ unsigned short to tree.
+ (cp_parser_range_for): Likewise. Set RANGE_FOR_UNROLL to just UNROLL
+ rather than build_int_cst from it.
+ (cp_convert_range_for, cp_parser_iteration_statement): Change UNROLL
+ type from unsigned short to tree.
+ (cp_parser_omp_loop_nest): Pass NULL_TREE rather than 0 to
+ cp_parser_range_for UNROLL argument.
+ (cp_parser_pragma_unroll): Return tree rather than unsigned short.
+ If parsed expression is type dependent, just return it, don't diagnose
+ issues with value if it is value dependent.
+ (cp_parser_pragma): Change UNROLL type from unsigned short to tree.
+ * semantics.cc (finish_while_stmt_cond): Change UNROLL type from
+ unsigned short to tree. Build ANNOTATE_EXPR with UNROLL as its last
+ operand rather than build_int_cst from it.
+ (finish_do_stmt, finish_for_cond): Likewise.
+ * pt.cc (tsubst_stmt) <case RANGE_FOR_STMT>: Change UNROLL type from
+ unsigned short to tree and set it to RECUR on RANGE_FOR_UNROLL (t).
+ (tsubst_expr) <case ANNOTATE_EXPR>: For annot_expr_unroll_kind repeat
+ checks on UNROLL value from cp_parser_pragma_unroll.
+
2023-12-02 Richard Sandiford <richard.sandiford@arm.com>
* cp-tree.h (cxx_attribute_table): Delete.
+2023-12-04 Gaius Mulley <gaiusmod2@gmail.com>
+
+ PR modula2/112825
+ * tools-src/makeSystem: Change all occurrences of -c to -S.
+
2023-11-01 Gaius Mulley <gaiusmod2@gmail.com>
PR modula2/102989
+2023-12-04 Jason Merrill <jason@redhat.com>
+
+ * g++.dg/cpp0x/constexpr-noreturn1.C: New test.
+
+2023-12-04 Robin Dapp <rdapp@ventanamicro.com>
+
+ * gcc.target/riscv/rvv/autovec/binop/copysign-zvfh-run.c:
+ Replace riscv_zvfh_hw with riscv_zvfh.
+ * gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/cond/cond_copysign-zvfh-run.c:
+ Ditto.
+ * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c:
+ Ditto.
+ * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-6.c: Allow
+ overriding N.
+ * gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c: Replace
+ riscv zvfh_hw with riscv_zvfh.
+ * gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-1.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-10.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-11.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-12.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-2.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-3.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-5.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-6.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-7.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/widen/widen_run_zvfh-8.c: Ditto.
+ * lib/target-supports.exp: Remove riscv_vector_hw and
+ riscv_zvfh_hw.
+
+2023-12-04 Robin Dapp <rdapp@ventanamicro.com>
+
+ * gcc.target/riscv/rvv/autovec/pr112552.c: Add
+ -Wno-incompatible-pointer-types.
+ * gcc.target/riscv/rvv/autovec/struct/struct_vect_run-10.c:
+ Add -std=gnu99.
+
+2023-12-04 Robin Dapp <rdapp@ventanamicro.com>
+
+ * gcc.target/riscv/rvv/base/cpymem-strategy-1.c: Change to
+ -mstringop-strategy.
+ * gcc.target/riscv/rvv/base/cpymem-strategy-2.c: Ditto.
+ * gcc.target/riscv/rvv/base/cpymem-strategy-3.c: Ditto.
+ * gcc.target/riscv/rvv/base/cpymem-strategy-4.c: Ditto.
+ * gcc.target/riscv/rvv/base/cpymem-strategy-5.c: Ditto.
+
+2023-12-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
+
+ PR target/112431
+ * gcc.target/riscv/rvv/base/pr112431-34.c: New test.
+
+2023-12-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
+
+ PR target/112431
+ * gcc.target/riscv/rvv/base/pr112431-37.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-38.c: New test.
+
+2023-12-04 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/112818
+ * gcc.dg/vect/pr112818.c: New testcase.
+
+2023-12-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
+
+ * g++.target/riscv/rvv/autovec/bug-01.C: Moved to...
+ * g++.target/riscv/rvv/autovec/bug-1.C: ...here.
+
+2023-12-04 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/112827
+ * gcc.dg/torture/pr112827-1.c: New testcase.
+ * gcc.dg/torture/pr112827-2.c: Likewise.
+
+2023-12-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
+
+ PR target/112431
+ * gcc.target/riscv/rvv/base/pr112431-35.c: New test.
+ * gcc.target/riscv/rvv/base/pr112431-36.c: New test.
+
+2023-12-04 Indu Bhagat <indu.bhagat@oracle.com>
+
+ PR debug/112656
+ * gcc.dg/debug/btf/btf-function-7.c: New test.
+
+2023-12-04 Indu Bhagat <indu.bhagat@oracle.com>
+
+ PR debug/112768
+ * gcc.dg/debug/btf/btf-function-6.c: Empty string expected with
+ BTF_KIND_FUNC_PROTO.
+
+2023-12-04 Pan Li <pan2.li@intel.com>
+
+ PR target/112813
+ * gcc.target/riscv/rvv/vsetvl/pr112813-1.c: New test.
+
+2023-12-04 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/112837
+ * gcc.dg/pr112837.c: New test.
+
+2023-12-04 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/112816
+ * gcc.target/i386/sse2-pr112816.c: New test.
+
+2023-12-04 Jakub Jelinek <jakub@redhat.com>
+
+ PR c++/112795
+ * g++.dg/ext/unroll-5.C: New test.
+ * g++.dg/ext/unroll-6.C: New test.
+
+2023-12-04 Feng Wang <wangfeng@eswincomputing.com>
+
+ * gcc.target/riscv/zvkn-1.c: Replace zvbb with zvkb.
+ * gcc.target/riscv/zvkn.c: Ditto.
+ * gcc.target/riscv/zvknc-1.c:Ditto.
+ * gcc.target/riscv/zvknc-2.c:Ditto.
+ * gcc.target/riscv/zvknc.c: Ditto.
+ * gcc.target/riscv/zvkng-1.c:Ditto.
+ * gcc.target/riscv/zvkng-2.c:Ditto.
+ * gcc.target/riscv/zvkng.c: Ditto.
+ * gcc.target/riscv/zvks-1.c: Ditto.
+ * gcc.target/riscv/zvks.c: Ditto.
+ * gcc.target/riscv/zvksc-1.c:Ditto.
+ * gcc.target/riscv/zvksc-2.c:Ditto.
+ * gcc.target/riscv/zvksc.c: Ditto.
+ * gcc.target/riscv/zvksg-1.c:Ditto.
+ * gcc.target/riscv/zvksg-2.c:Ditto.
+ * gcc.target/riscv/zvksg.c: Ditto.
+
+2023-12-04 Fei Gao <gaofei@eswincomputing.com>
+ Xiao Zeng <zengxiao@eswincomputing.com>
+
+ * gcc.target/riscv/zicond-sfb-primitiveSemantics.c: New test.
+
+2023-12-04 Kito Cheng <kito.cheng@sifive.com>
+
+ * gcc.target/riscv/mcpu-sifive-x280.c: New test.
+
+2023-12-04 Hu, Lin1 <lin1.hu@intel.com>
+
+ * gcc.target/i386/user_msr-1.c: Correct the MSR index for give the user
+ an proper example.
+
2023-12-03 Jakub Jelinek <jakub@redhat.com>
PR middle-end/112406
projects / thirdparty / gcc.git / commitdiff
