i2c: tegra: Add support for SW mutex register

Add support for SW mutex register introduced in Tegra264 to provide
an option to share the interface between multiple firmwares and/or
VMs. This involves following steps:

 - A firmware/OS writes its unique ID to the mutex REQUEST field.
 - Ownership is established when reading the GRANT field returns the
   same ID.
 - If GRANT shows a different non-zero ID, the firmware/OS retries
   until timeout.
 - After completing access, it releases the mutex by writing 0.

However, the hardware does not ensure any protection based on the
values. The driver/firmware should honor the peer who already holds
the mutex.

Signed-off-by: Kartik Rajput <kkartik@nvidia.com>
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 3cbda036331622a698db25bbd5f70ea1c6e9abdf..84f2d5f4b794c8061f898e5b9fb956646a8f292d 100644 (file)
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -137,6 +137,14 @@
 
 #define I2C_MASTER_RESET_CNTRL                 0x0a8
 
+#define I2C_SW_MUTEX                           0x0ec
+#define I2C_SW_MUTEX_REQUEST                   GENMASK(3, 0)
+#define I2C_SW_MUTEX_GRANT                     GENMASK(7, 4)
+#define I2C_SW_MUTEX_ID_CCPLEX                 9
+
+/* SW mutex acquire timeout value in microseconds. */
+#define I2C_SW_MUTEX_TIMEOUT_US                        (25 * USEC_PER_MSEC)
+
 /* configuration load timeout in microseconds */
 #define I2C_CONFIG_LOAD_TIMEOUT                        1000000
 
@@ -214,6 +222,7 @@ enum msg_end_type {
  * @has_interface_timing_reg: Has interface timing register to program the tuned
  *             timing settings.
  * @enable_hs_mode_support: Enable support for high speed (HS) mode transfers.
+ * @has_mutex: Has mutex register for mutual exclusion with other firmwares or VMs.
  */
 struct tegra_i2c_hw_feature {
        bool has_continue_xfer_support;
@@ -244,6 +253,7 @@ struct tegra_i2c_hw_feature {
        u32 setup_hold_time_hs_mode;
        bool has_interface_timing_reg;
        bool enable_hs_mode_support;
+       bool has_mutex;
 };
 
 /**
@@ -388,6 +398,76 @@ static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
        readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 }
 
+static bool tegra_i2c_mutex_acquired(struct tegra_i2c_dev *i2c_dev)
+{
+       unsigned int reg = tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX);
+       u32 val, id;
+
+       val = readl(i2c_dev->base + reg);
+       id = FIELD_GET(I2C_SW_MUTEX_GRANT, val);
+
+       return id == I2C_SW_MUTEX_ID_CCPLEX;
+}
+
+static bool tegra_i2c_mutex_trylock(struct tegra_i2c_dev *i2c_dev)
+{
+       unsigned int reg = tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX);
+       u32 val, id;
+
+       val = readl(i2c_dev->base + reg);
+       id = FIELD_GET(I2C_SW_MUTEX_GRANT, val);
+       if (id != 0 && id != I2C_SW_MUTEX_ID_CCPLEX)
+               return false;
+
+       val = FIELD_PREP(I2C_SW_MUTEX_REQUEST, I2C_SW_MUTEX_ID_CCPLEX);
+       writel(val, i2c_dev->base + reg);
+
+       return tegra_i2c_mutex_acquired(i2c_dev);
+}
+
+static int tegra_i2c_mutex_lock(struct tegra_i2c_dev *i2c_dev)
+{
+       bool locked;
+       int ret;
+
+       if (!i2c_dev->hw->has_mutex)
+               return 0;
+
+       if (i2c_dev->atomic_mode)
+               ret = read_poll_timeout_atomic(tegra_i2c_mutex_trylock, locked, locked,
+                                              USEC_PER_MSEC, I2C_SW_MUTEX_TIMEOUT_US,
+                                              false, i2c_dev);
+       else
+               ret = read_poll_timeout(tegra_i2c_mutex_trylock, locked, locked, USEC_PER_MSEC,
+                                       I2C_SW_MUTEX_TIMEOUT_US, false, i2c_dev);
+
+       if (ret)
+               dev_warn(i2c_dev->dev, "failed to acquire mutex\n");
+
+       return ret;
+}
+
+static int tegra_i2c_mutex_unlock(struct tegra_i2c_dev *i2c_dev)
+{
+       unsigned int reg = tegra_i2c_reg_addr(i2c_dev, I2C_SW_MUTEX);
+       u32 val, id;
+
+       if (!i2c_dev->hw->has_mutex)
+               return 0;
+
+       val = readl(i2c_dev->base + reg);
+
+       id = FIELD_GET(I2C_SW_MUTEX_GRANT, val);
+       if (id && id != I2C_SW_MUTEX_ID_CCPLEX) {
+               dev_warn(i2c_dev->dev, "unable to unlock mutex, mutex is owned by: %u\n", id);
+               return -EPERM;
+       }
+
+       writel(0, i2c_dev->base + reg);
+
+       return 0;
+}
+
 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 {
        u32 int_mask;
@@ -1443,6 +1523,10 @@ static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
                return ret;
        }
 
+       ret = tegra_i2c_mutex_lock(i2c_dev);
+       if (ret)
+               return ret;
+
        for (i = 0; i < num; i++) {
                enum msg_end_type end_type = MSG_END_STOP;
 
@@ -1472,6 +1556,7 @@ static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
                        break;
        }
 
+       ret = tegra_i2c_mutex_unlock(i2c_dev);
        pm_runtime_put(i2c_dev->dev);
 
        return ret ?: i;
@@ -1551,6 +1636,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
        .setup_hold_time_hs_mode = 0x0,
        .has_interface_timing_reg = false,
        .enable_hs_mode_support = false,
+       .has_mutex = false,
 };
 
 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
@@ -1580,6 +1666,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
        .setup_hold_time_hs_mode = 0x0,
        .has_interface_timing_reg = false,
        .enable_hs_mode_support = false,
+       .has_mutex = false,
 };
 
 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
@@ -1609,6 +1696,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
        .setup_hold_time_hs_mode = 0x0,
        .has_interface_timing_reg = false,
        .enable_hs_mode_support = false,
+       .has_mutex = false,
 };
 
 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
@@ -1638,6 +1726,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
        .setup_hold_time_hs_mode = 0x0,
        .has_interface_timing_reg = true,
        .enable_hs_mode_support = false,
+       .has_mutex = false,
 };
 
 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
@@ -1667,6 +1756,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
        .setup_hold_time_hs_mode = 0,
        .has_interface_timing_reg = true,
        .enable_hs_mode_support = false,
+       .has_mutex = false,
 };
 
 static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
@@ -1696,6 +1786,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
        .setup_hold_time_hs_mode = 0,
        .has_interface_timing_reg = true,
        .enable_hs_mode_support = false,
+       .has_mutex = false,
 };
 
 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
@@ -1727,6 +1818,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
        .setup_hold_time_hs_mode = 0x090909,
        .has_interface_timing_reg = true,
        .enable_hs_mode_support = true,
+       .has_mutex = false,
 };
 
 static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
@@ -1758,6 +1850,7 @@ static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
        .setup_hold_time_hs_mode = 0x030303,
        .has_interface_timing_reg = true,
        .enable_hs_mode_support = true,
+       .has_mutex = true,
 };
 
 static const struct of_device_id tegra_i2c_of_match[] = {