re PR rtl-optimization/47862 (Incorrect code for spilling a vector register)

        PR target/47862
        * config/rs6000/rs6000.h (HARD_REGNO_CALLER_SAVE_MODE): Define.

        * gcc.target/powerpc/pr47862.c: New.

From-SVN: r170749

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5c464c72c354557eeb66599f570c363e59b36999..c03813142a62adf9ef98745dc43817f0b7542f41 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2011-03-07  Pat Haugen <pthaugen@us.ibm.com>
+
+       Backport from mainline
+       2011-03-07  Pat Haugen <pthaugen@us.ibm.com>
+
+       PR target/47862
+       * config/rs6000/rs6000.h (HARD_REGNO_CALLER_SAVE_MODE): Define.
+
 2011-03-07  Mingjie Xing  <mingjie.xing@gmail.com>
 
        * doc/cfg.texi: Remove "See" before @ref.

diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 764ab56c464c0126752683d07dded3cb58cae4b9..596f8a82eaebd1d1a8c3da3ba1bd66f45a389431 100644 (file)
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1036,6 +1036,16 @@ extern unsigned rs6000_pointer_size;
 
 #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)]
 
+/* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate
+   enough space to account for vectors in FP regs. */
+#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE)        \
+  (TARGET_VSX                                          \
+   && ((MODE) == VOIDmode || VSX_VECTOR_MODE (MODE)    \
+       || ALTIVEC_VECTOR_MODE (MODE))                  \
+   && FP_REGNO_P (REGNO)                               \
+   ? V2DFmode                                          \
+   : choose_hard_reg_mode ((REGNO), (NREGS), false))
+
 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE)                    \
   (((TARGET_32BIT && TARGET_POWERPC64                                  \
      && (GET_MODE_SIZE (MODE) > 4)                                     \

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 71b2df3c13d17c8acf8e17bd92312e43d64fe153..8159f7d5e36ca0950b2a1a99ce5bb544a1b77efe 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2011-03-07  Pat Haugen <pthaugen@us.ibm.com>
+
+       Backport from mainline
+       2011-03-07  Pat Haugen <pthaugen@us.ibm.com>
+
+       PR target/47862
+       * gcc.target/powerpc/pr47862.c: New.
+
 2011-03-06  Jerry DeLisle  <jvdelisle@gcc.gnu.org>
 
        Backport from mainline

diff --git a/gcc/testsuite/gcc.target/powerpc/pr47862.c b/gcc/testsuite/gcc.target/powerpc/pr47862.c
new file mode 100644 (file)
index 0000000..528cace
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr47862.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7" } */
+/* { dg-final { scan-assembler-not "stfd" } } */
+
+/* PR 47862: Verify caller-save spill of vectors in FP regs do not use
+   legacy FP insns, which spill only half the vector.  */
+extern vector double dd[15];
+
+vector double foo() {
+  vector double a,b,c,d,e,f,g,h,i,j,k,l,m,n;
+
+  a=dd[1]; b=dd[2]; c=dd[3]; d=dd[4]; e=dd[5]; f=dd[6]; g=dd[7]; h=dd[8]; i=dd[9];
+  j=dd[10]; k=dd[11]; l=dd[12]; m=dd[13]; n=dd[14];
+  bar();
+  return (a+b+c+d+e+f+g+h+i+j+k+l+m+n);
+}
+