clk: mediatek: add array size field for id_offs_map

Add id_offs_map_size field to struct mtk_clk_tree and populate it for
all existing drivers.

Currently, there is no bounds checking when accessing the id_offs_map
array. Adding this field will allow for bounds checking in the future.

Signed-off-by: David Lechner <dlechner@baylibre.com>

diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
index 5a60a86233e8e847ce6284c2122c69293b597aa6..eca8352d8e648db54bd9d4e8cc13b2132d6f81f7 100644 (file)
--- a/drivers/clk/mediatek/clk-mt7623.c
+++ b/drivers/clk/mediatek/clk-mt7623.c
@@ -996,6 +996,7 @@ static const struct mtk_gate hif_cgs[] = {
 static const struct mtk_clk_tree mt7623_apmixedsys_clk_tree = {
        .xtal2_rate = 26 * MHZ,
        .id_offs_map = pll_id_offs_map,
+       .id_offs_map_size = ARRAY_SIZE(pll_id_offs_map),
        .plls = apmixed_plls,
        .num_plls = ARRAY_SIZE(apmixed_plls),
 };
@@ -1003,6 +1004,7 @@ static const struct mtk_clk_tree mt7623_apmixedsys_clk_tree = {
 static const struct mtk_clk_tree mt7623_topckgen_clk_tree = {
        .xtal_rate = 26 * MHZ,
        .id_offs_map = top_id_offs_map,
+       .id_offs_map_size = ARRAY_SIZE(top_id_offs_map),
        .fdivs_offs = top_id_offs_map[CLK_TOP_SYSPLL],
        .muxes_offs = top_id_offs_map[CLK_TOP_AXI_SEL],
        .fclks = top_fixed_clks,
@@ -1063,6 +1065,7 @@ static int mt7623_infracfg_probe(struct udevice *dev)
 
 static const struct mtk_clk_tree mt7623_clk_peri_tree = {
        .id_offs_map = peri_id_offs_map,
+       .id_offs_map_size = ARRAY_SIZE(peri_id_offs_map),
        .muxes_offs = peri_id_offs_map[CLK_PERI_UART0_SEL],
        .gates_offs = peri_id_offs_map[CLK_PERI_NFI],
        .muxes = peri_muxes,

diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c
index f7c04047f4dc07ed43723ae57fc9b24acb855768..a4cbb3213e376392689e6f163b83fa73cfdc170e 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8188.c
+++ b/drivers/clk/mediatek/clk-mt8188.c
@@ -1360,6 +1360,7 @@ static const struct mtk_clk_tree mt8188_topckgen_clk_tree = {
        .xtal_rate = 26 * MHZ,
        .xtal2_rate = 26 * MHZ,
        .id_offs_map = mt8188_id_offs_map,
+       .id_offs_map_size = ARRAY_SIZE(mt8188_id_offs_map),
        .fdivs_offs = 8, /* CLK_TOP_MAINPLL_D3 */
        .muxes_offs = 87, /* CLK_TOP_AXI */
        .fclks = top_fixed_clks,

diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 7bd432cb93dbb67c78c071f4c54b7c44cd7e5b88..8a1cb0839a016a14d3d83fdf2f7a25144cf6e9fe 100644 (file)
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -252,6 +252,7 @@ struct mtk_clk_tree {
         * ID for factor, mux and gates.
         */
        const int *id_offs_map; /* optional, table clk.h to driver ID */
+       const int id_offs_map_size;
        const int fdivs_offs;
        const int muxes_offs;
        const int gates_offs;