drm/amdgpu: Add virt command to send VF ras command

Add virt command and interface to send VF ras command.

Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 47a6ce4fdc7444cddc52948d256ca55169d017ec..2d48818773c0c0163369ae16cf319f7f25b80ee0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -1845,3 +1845,28 @@ int amdgpu_virt_check_vf_critical_region(struct amdgpu_device *adev, u64 addr, b
 
        return r;
 }
+
+static int req_remote_ras_cmd(struct amdgpu_device *adev,
+                       u32 param1, u32 param2, u32 param3)
+{
+       struct amdgpu_virt *virt = &adev->virt;
+
+       if (virt->ops && virt->ops->req_remote_ras_cmd)
+               return virt->ops->req_remote_ras_cmd(adev, param1, param2, param3);
+       return -ENOENT;
+}
+
+int amdgpu_virt_send_remote_ras_cmd(struct amdgpu_device *adev,
+               uint64_t buf, uint32_t buf_len)
+{
+       uint64_t gpa = buf;
+       int ret = -EIO;
+
+       if (down_read_trylock(&adev->reset_domain->sem)) {
+               ret = req_remote_ras_cmd(adev,
+                       lower_32_bits(gpa), upper_32_bits(gpa), buf_len);
+               up_read(&adev->reset_domain->sem);
+       }
+
+       return ret;
+}

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index 01d5bca2dee1655c8576593292888d3e89fc4063..608d966701a488493a01ce252eec2047c169aae3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -105,6 +105,8 @@ struct amdgpu_virt_ops {
        int (*req_ras_cper_dump)(struct amdgpu_device *adev, u64 vf_rptr);
        int (*req_bad_pages)(struct amdgpu_device *adev);
        int (*req_ras_chk_criti)(struct amdgpu_device *adev, u64 addr);
+       int (*req_remote_ras_cmd)(struct amdgpu_device *adev,
+                       u32 param1, u32 param2, u32 param3);
 };
 
 /*
@@ -483,4 +485,6 @@ bool amdgpu_virt_ras_telemetry_block_en(struct amdgpu_device *adev,
                                        enum amdgpu_ras_block block);
 void amdgpu_virt_request_bad_pages(struct amdgpu_device *adev);
 int amdgpu_virt_check_vf_critical_region(struct amdgpu_device *adev, u64 addr, bool *hit);
+int amdgpu_virt_send_remote_ras_cmd(struct amdgpu_device *adev,
+               uint64_t buf, uint32_t buf_len);
 #endif

diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
index e7cd07383d56e9b362e7166c08ea3d1a4958b899..78408b257afc77c7bd2154c6653fb83bbe9fa352 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
@@ -209,6 +209,9 @@ send_request:
        case IDH_REQ_RAS_CHK_CRITI:
                event = IDH_REQ_RAS_CHK_CRITI_READY;
                break;
+       case IDH_REQ_RAS_REMOTE_CMD:
+               event = IDH_REQ_RAS_REMOTE_CMD_READY;
+               break;
        default:
                break;
        }
@@ -585,6 +588,13 @@ static int xgpu_nv_check_vf_critical_region(struct amdgpu_device *adev, u64 addr
                adev, IDH_REQ_RAS_CHK_CRITI, addr_hi, addr_lo, 0);
 }
 
+static int xgpu_nv_req_remote_ras_cmd(struct amdgpu_device *adev,
+               u32 param1, u32 param2, u32 param3)
+{
+       return xgpu_nv_send_access_requests_with_param(
+               adev, IDH_REQ_RAS_REMOTE_CMD, param1, param2, param3);
+}
+
 const struct amdgpu_virt_ops xgpu_nv_virt_ops = {
        .req_full_gpu   = xgpu_nv_request_full_gpu_access,
        .rel_full_gpu   = xgpu_nv_release_full_gpu_access,
@@ -598,5 +608,6 @@ const struct amdgpu_virt_ops xgpu_nv_virt_ops = {
        .req_ras_err_count = xgpu_nv_req_ras_err_count,
        .req_ras_cper_dump = xgpu_nv_req_ras_cper_dump,
        .req_bad_pages = xgpu_nv_req_ras_bad_pages,
-       .req_ras_chk_criti = xgpu_nv_check_vf_critical_region
+       .req_ras_chk_criti = xgpu_nv_check_vf_critical_region,
+       .req_remote_ras_cmd = xgpu_nv_req_remote_ras_cmd,
 };

diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h
index c1083e5e41e0299991444c660efaf430c153cb61..dc57a4f697eec0f14127b5c1313ca397395529d9 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h
@@ -43,7 +43,8 @@ enum idh_request {
        IDH_REQ_RAS_ERROR_COUNT = 203,
        IDH_REQ_RAS_CPER_DUMP = 204,
        IDH_REQ_RAS_BAD_PAGES = 205,
-       IDH_REQ_RAS_CHK_CRITI = 206
+       IDH_REQ_RAS_CHK_CRITI = 206,
+       IDH_REQ_RAS_REMOTE_CMD = 207,
 };
 
 enum idh_event {
@@ -64,6 +65,7 @@ enum idh_event {
        IDH_RAS_BAD_PAGES_NOTIFICATION = 16,
        IDH_UNRECOV_ERR_NOTIFICATION = 17,
        IDH_REQ_RAS_CHK_CRITI_READY = 18,
+       IDH_REQ_RAS_REMOTE_CMD_READY = 19,
 
        IDH_TEXT_MESSAGE = 255,
 };