]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
accel/qaic: kcalloc + kzalloc to kzalloc
authorRosen Penev <rosenp@gmail.com>
Wed, 1 Apr 2026 22:06:43 +0000 (15:06 -0700)
committerJeff Hugo <jeff.hugo@oss.qualcomm.com>
Tue, 12 May 2026 16:20:40 +0000 (10:20 -0600)
Consolidate the two-element allocation into a single allocation using a
flexible array member. This reduces memory fragmentation and simplifies
the error path by eliminating the need to check for allocation failure
between the two allocations.

Add __counted_by for runtime bounds checking.

Signed-off-by: Rosen Penev <rosenp@gmail.com>
Tested-by: Youssef Samir <youssef.abdulrahman@oss.qualcomm.com>
Reviewed-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com>
Signed-off-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com>
Link: https://patch.msgid.link/20260401220643.12802-1-rosenp@gmail.com
drivers/accel/qaic/qaic.h
drivers/accel/qaic/qaic_drv.c

index 83948358ada1f16bfbbe224a8132e75cdd0bd4fc..02ca99000e2ae76b8a2ed7a63b9e337de96d9ac0 100644 (file)
@@ -151,8 +151,6 @@ struct qaic_device {
        struct list_head        cntl_xfer_list;
        /* Synchronizes MHI control device transactions and its xfer list */
        struct mutex            cntl_mutex;
-       /* Array of DBC struct of this device */
-       struct dma_bridge_chan  *dbc;
        /* Work queue for tasks related to MHI control device */
        struct workqueue_struct *cntl_wq;
        /* Synchronizes all the users of device during cleanup */
@@ -205,6 +203,8 @@ struct qaic_device {
        void                    *ssr_mhi_buf;
        /* DBC which is under SSR. Sentinel U32_MAX would mean that no SSR in progress */
        u32                     ssr_dbc;
+       /* Array of DBC struct of this device */
+       struct dma_bridge_chan  dbc[] __counted_by(num_dbc);
 };
 
 struct qaic_drm_device {
index 1c7c57dabcd6d1ee8b47907aae9b9891f430e5e6..0acf6cdd44f81430ec52c7120b8b50c60721a615 100644 (file)
@@ -43,6 +43,7 @@ MODULE_IMPORT_NS("DMA_BUF");
 #define QAIC_DESC                      "Qualcomm Cloud AI Accelerators"
 #define CNTL_MAJOR                     5
 #define CNTL_MINOR                     0
+#define DBC_NUM                                16
 
 struct qaic_device_config {
        /* Indicates the AIC family the device belongs to */
@@ -405,15 +406,12 @@ static struct qaic_device *create_qdev(struct pci_dev *pdev,
        struct drm_device *drm;
        int i, ret;
 
-       qdev = devm_kzalloc(dev, sizeof(*qdev), GFP_KERNEL);
+       qdev = devm_kzalloc(dev, struct_size(qdev, dbc, DBC_NUM), GFP_KERNEL);
        if (!qdev)
                return NULL;
 
+       qdev->num_dbc = DBC_NUM;
        qdev->dev_state = QAIC_OFFLINE;
-       qdev->num_dbc = 16;
-       qdev->dbc = devm_kcalloc(dev, qdev->num_dbc, sizeof(*qdev->dbc), GFP_KERNEL);
-       if (!qdev->dbc)
-               return NULL;
 
        qddev = devm_drm_dev_alloc(&pdev->dev, &qaic_accel_driver, struct qaic_drm_device, drm);
        if (IS_ERR(qddev))