struct list_head cntl_xfer_list;
/* Synchronizes MHI control device transactions and its xfer list */
struct mutex cntl_mutex;
- /* Array of DBC struct of this device */
- struct dma_bridge_chan *dbc;
/* Work queue for tasks related to MHI control device */
struct workqueue_struct *cntl_wq;
/* Synchronizes all the users of device during cleanup */
void *ssr_mhi_buf;
/* DBC which is under SSR. Sentinel U32_MAX would mean that no SSR in progress */
u32 ssr_dbc;
+ /* Array of DBC struct of this device */
+ struct dma_bridge_chan dbc[] __counted_by(num_dbc);
};
struct qaic_drm_device {
#define QAIC_DESC "Qualcomm Cloud AI Accelerators"
#define CNTL_MAJOR 5
#define CNTL_MINOR 0
+#define DBC_NUM 16
struct qaic_device_config {
/* Indicates the AIC family the device belongs to */
struct drm_device *drm;
int i, ret;
- qdev = devm_kzalloc(dev, sizeof(*qdev), GFP_KERNEL);
+ qdev = devm_kzalloc(dev, struct_size(qdev, dbc, DBC_NUM), GFP_KERNEL);
if (!qdev)
return NULL;
+ qdev->num_dbc = DBC_NUM;
qdev->dev_state = QAIC_OFFLINE;
- qdev->num_dbc = 16;
- qdev->dbc = devm_kcalloc(dev, qdev->num_dbc, sizeof(*qdev->dbc), GFP_KERNEL);
- if (!qdev->dbc)
- return NULL;
qddev = devm_drm_dev_alloc(&pdev->dev, &qaic_accel_driver, struct qaic_drm_device, drm);
if (IS_ERR(qddev))