riscv: hwprobe: export Zilsd and Zclsd ISA extensions

Export Zilsd and Zclsd ISA extensions through hwprobe.

Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
Reviewed-by: Nutty Liu <nutty.liu@hotmail.com>
Link: https://patch.msgid.link/20250826162939.1494021-4-pincheng.plct@isrc.iscas.ac.cn
[pjw@kernel.org: fixed whitespace; updated to apply]
Signed-off-by: Paul Walmsley <pjw@kernel.org>

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 06c5280b728a27dd5370e29d31384d720e7f0ddf..641ec4abb90622a579838a4d17a87a8518886c72 100644 (file)
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -281,6 +281,14 @@ The following keys are defined:
   * :c:macro:`RISCV_HWPROBE_EXT_ZICBOP`: The Zicbop extension is supported, as
        ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZILSD`: The Zilsd extension is supported as
+       defined in the RISC-V ISA manual starting from commit f88abf1 ("Integrating
+       load/store pair for RV32 with the main manual") of the riscv-isa-manual.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZCLSD`: The Zclsd extension is supported as
+       defined in the RISC-V ISA manual starting from commit f88abf1 ("Integrating
+       load/store pair for RV32 with the main manual") of the riscv-isa-manual.
+
 * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated.  Returns similar values to
      :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
      mistakenly classified as a bitmask rather than a value.

diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 1edea2331b8bda8307adb95ba515249367c6a122..cd3c126730c33c380b3209749cb6edaf02d4227d 100644 (file)
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -84,6 +84,9 @@ struct riscv_hwprobe {
 #define                RISCV_HWPROBE_EXT_ZABHA         (1ULL << 58)
 #define                RISCV_HWPROBE_EXT_ZALASR        (1ULL << 59)
 #define                RISCV_HWPROBE_EXT_ZICBOP        (1ULL << 60)
+#define                RISCV_HWPROBE_EXT_ZILSD         (1ULL << 61)
+#define                RISCV_HWPROBE_EXT_ZCLSD         (1ULL << 62)
+
 #define RISCV_HWPROBE_KEY_CPUPERF_0    5
 #define                RISCV_HWPROBE_MISALIGNED_UNKNOWN        (0 << 0)
 #define                RISCV_HWPROBE_MISALIGNED_EMULATED       (1 << 0)

diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 0f701ace3bb9a09f2ffd26e7e2da8dd7d68b7c6f..e6787ba7f2fc411b69092fbf06103790ef08f045 100644 (file)
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -121,6 +121,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
                EXT_KEY(ZBS);
                EXT_KEY(ZCA);
                EXT_KEY(ZCB);
+               EXT_KEY(ZCLSD);
                EXT_KEY(ZCMOP);
                EXT_KEY(ZICBOM);
                EXT_KEY(ZICBOP);
@@ -130,6 +131,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
                EXT_KEY(ZIHINTNTL);
                EXT_KEY(ZIHINTPAUSE);
                EXT_KEY(ZIHPM);
+               EXT_KEY(ZILSD);
                EXT_KEY(ZIMOP);
                EXT_KEY(ZKND);
                EXT_KEY(ZKNE);