]> git.ipfire.org Git - thirdparty/u-boot.git/commitdiff
arm: pinctrl: Define .mux_mask field for NXP's SoC
authorLukasz Majewski <lukma@denx.de>
Fri, 27 Jun 2025 05:49:43 +0000 (07:49 +0200)
committerFabio Estevam <festevam@gmail.com>
Sun, 29 Jun 2025 13:07:55 +0000 (10:07 -0300)
The commit e8a9521e649f
("vf500/vf610: synchronise device trees with linux")
has synchronized U-Boot's DTS with v5.19 Linux kernel.
It turned out that in Linux's upstream iomuxc node description the
'fsl,mux_mask' was missing, so the U-Boot's pinctrl driver for NXP's
Vybrid SoC was not working properly.

As by default the mux mask was set to 0, for example the vf610 based
boards (like BK4) were bricked, due to misconfiguration of gpio at
early boot stage.

The fix for all NXP eligible boards is to define .mux_mask field for
soc specific *pinctrl_soc_info structure and use it directly in pinctrl
MMIO driver, without the need to read the "fsl,mux_mask" property from
device tree.

This change brings the NXP's pinctrl driver in U-Boot closer to Linux
upstream one.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com> #for i.MX8ULP
arch/arm/dts/imx8ulp-evk-u-boot.dtsi
arch/arm/dts/imxrt1020.dtsi
arch/arm/dts/imxrt1170.dtsi
drivers/pinctrl/nxp/pinctrl-imx-mmio.c
drivers/pinctrl/nxp/pinctrl-imx8ulp.c
drivers/pinctrl/nxp/pinctrl-imxrt.c
drivers/pinctrl/nxp/pinctrl-vf610.c

index f67fe166d31f09c8e9c800ad7894cadad4d7abb0..845fe2059258738406f77f58e0381bc82a21f2b2 100644 (file)
@@ -28,7 +28,6 @@
 
 &iomuxc1 {
        bootph-pre-ram;
-       fsl,mux_mask = <0xf00>;
 };
 
 &pinctrl_lpuart5 {
index 13511ebb18ecbc6e36b269f396effc66bf374d8e..336aeedb2ce363ad5309d1c0a29c7b5bf273cf20 100644 (file)
@@ -64,7 +64,6 @@
                iomuxc: iomuxc@401f8000 {
                        compatible = "fsl,imxrt-iomuxc";
                        reg = <0x401f8000 0x4000>;
-                       fsl,mux_mask = <0x7>;
                };
 
                anatop: anatop@400d8000 {
index 08665eaf06a03dd27031770a3f8fa4871537d914..7566402353a678b2f9eba0d19bcd1ae859a0e89f 100644 (file)
@@ -77,7 +77,6 @@
                iomuxc: iomuxc@400e8000 {
                        compatible = "fsl,imxrt-iomuxc";
                        reg = <0x400e8000 0x4000>;
-                       fsl,mux_mask = <0x7>;
                };
 
                anatop: anatop@40c84000 {
index 6ee108a0120fce8d903cedb08906b32ee47a3482..2f4228a9fc5f960da4b461d01ac49ddbeec0b92d 100644 (file)
@@ -187,7 +187,6 @@ int imx_pinctrl_probe_mmio(struct udevice *dev)
                return -ENOMEM;
        priv->info = info;
 
-       info->mux_mask = ofnode_read_u32_default(node, "fsl,mux_mask", 0);
        /*
         * Refer to linux documentation for details:
         * Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
index 2df63625191932c8ed12d16e814c1991857a1588..3e8c080d3fd0096dcd99a2dba46b59c2cea2c786 100644 (file)
 
 static struct imx_pinctrl_soc_info imx8ulp_pinctrl_soc_info0 = {
        .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG | CFG_IBE_OBE,
+       .mux_mask = 0xf00,
 };
 
 static struct imx_pinctrl_soc_info imx8ulp_pinctrl_soc_info1 = {
        .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG | CFG_IBE_OBE,
+       .mux_mask = 0xf00,
 };
 
 static const struct udevice_id imx8ulp_pinctrl_match[] = {
index 39000ceb9230e0e58e37b53e852d52a3914dd976..7e55d5962480c830b5493dda5d0070c20f74873a 100644 (file)
@@ -11,6 +11,7 @@
 
 static struct imx_pinctrl_soc_info imxrt_pinctrl_soc_info = {
        .flags = ZERO_OFFSET_VALID,
+       .mux_mask = 0x7,
 };
 
 static const struct udevice_id imxrt_pinctrl_match[] = {
index cbff8dcefd8c4bd884800ccd1e5f7dd497f976cd..7d1b95eaa057baccf229fda811c586d5c16e0c11 100644 (file)
@@ -11,6 +11,7 @@
 
 static struct imx_pinctrl_soc_info vf610_pinctrl_soc_info = {
        .flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID,
+       .mux_mask = 0x700000,
 };
 
 static const struct udevice_id vf610_pinctrl_match[] = {