media: rzv2h-ivc: Fix AXIRX_VBLANK register write

According to the documentation there are writable reserved bits in the
register and those should not be set to 0. So use `rzv2h_ivc_update_bits()`
with a proper bitmask.

Cc: stable@vger.kernel.org
Fixes: f0b3984d821b ("media: platform: Add Renesas Input Video Control block driver")
Reviewed-by: Daniel Scally <dan.scally@ideasonboard.com>
Signed-off-by: Barnabás Pőcze <barnabas.pocze+renesas@ideasonboard.com>
Signed-off-by: Jacopo Mondi <jacopo.mondi+renesas@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>

diff --git a/drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc-video.c b/drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc-video.c
index 1e016b17dceebbc8950bdddce0c8c2a26f61bc33..bfe5b0c7045ea428df113903c3451084832aead3 100644 (file)
--- a/drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc-video.c
+++ b/drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc-video.c
@@ -7,6 +7,7 @@
 
 #include "rzv2h-ivc.h"
 
+#include <linux/bitfield.h>
 #include <linux/cleanup.h>
 #include <linux/iopoll.h>
 #include <linux/lockdep.h>
@@ -235,8 +236,10 @@ static void rzv2h_ivc_format_configure(struct rzv2h_ivc *ivc)
        hts = pix->width + RZV2H_IVC_FIXED_HBLANK;
        vblank = RZV2H_IVC_MIN_VBLANK(hts);
 
-       rzv2h_ivc_write(ivc, RZV2H_IVC_REG_AXIRX_BLANK,
-                       RZV2H_IVC_VBLANK(vblank));
+       rzv2h_ivc_update_bits(ivc, RZV2H_IVC_REG_AXIRX_BLANK,
+                             RZV2H_IVC_AXIRX_BLANK_FIELD_VBLANK,
+                             FIELD_PREP(RZV2H_IVC_AXIRX_BLANK_FIELD_VBLANK,
+                                        vblank));
 }
 
 static void rzv2h_ivc_return_buffers(struct rzv2h_ivc *ivc,

diff --git a/drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc.h b/drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc.h
index 3bcaab990b0f8d18d78e34388f1f529f5543999b..4ef44c8b46569430b4492f7cfeb724c16fd27ad3 100644 (file)
--- a/drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc.h
+++ b/drivers/media/platform/renesas/rzv2h-ivc/rzv2h-ivc.h
@@ -34,7 +34,7 @@
 #define RZV2H_IVC_REG_AXIRX_HSIZE                      0x0020
 #define RZV2H_IVC_REG_AXIRX_VSIZE                      0x0024
 #define RZV2H_IVC_REG_AXIRX_BLANK                      0x0028
-#define RZV2H_IVC_VBLANK(x)                            ((x) << 16)
+#define RZV2H_IVC_AXIRX_BLANK_FIELD_VBLANK             GENMASK(25, 16)
 #define RZV2H_IVC_REG_AXIRX_STRD                       0x0030
 #define RZV2H_IVC_REG_AXIRX_ISSU                       0x0040
 #define RZV2H_IVC_REG_AXIRX_ERACT                      0x0048