arm64: dts: bst: enable eMMC controller in C1200

Add mmc0 node for the DWCMSHC SDHCI controller with basic configuration
(disabled by default) and fixed clock definition in bstc1200.dtsi.

Enable mmc0 with board-specific configuration including 8-bit bus
width and reserved SRAM bounce buffer on the CDCU1.0 ADAS 4C2G board.

The bounce buffer in reserved SRAM addresses hardware constraints
where the eMMC controller cannot access main system memory through
SMMU due to a hardware bug, and all DRAM is located outside the
4GB boundary.

Signed-off-by: Albert Yang <yangzh0906@thundersoft.com>
Acked-by: Gordon Ge <gordon.ge@bst.ai>
Signed-off-by: Gordon Ge <gordon.ge@bst.ai>

diff --git a/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts
index 5eb9ef369d8c943ccbc80cd6514f0d87085d76d8..178ad4bf4f0aacf831a61af07ad151a70e075749 100644 (file)
--- a/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts
+++ b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts
@@ -17,6 +17,25 @@
                      <0x8 0xc0000000 0x1 0x0>,
                      <0xc 0x00000000 0x0 0x40000000>;
        };
+
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               mmc0_reserved: mmc0-reserved@5160000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x0 0x5160000 0x0 0x10000>;
+                       no-map;
+               };
+       };
+};
+
+&mmc0 {
+       bus-width = <8>;
+       memory-region = <&mmc0_reserved>;
+       non-removable;
+       status = "okay";
 };
 
 &uart0 {

diff --git a/arch/arm64/boot/dts/bst/bstc1200.dtsi b/arch/arm64/boot/dts/bst/bstc1200.dtsi
index dd13c6bfc3c89a6c626c1830dfcad176fa9210d6..9660d8396e275945b27846c80dde79478c16ae76 100644 (file)
--- a/arch/arm64/boot/dts/bst/bstc1200.dtsi
+++ b/arch/arm64/boot/dts/bst/bstc1200.dtsi
@@ -7,6 +7,12 @@
        #address-cells = <2>;
        #size-cells = <2>;
 
+       clk_mmc: clock-4000000 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <4000000>;
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -72,6 +78,18 @@
                        status = "disabled";
                };
 
+               mmc0: mmc@22200000 {
+                       compatible = "bst,c1200-sdhci";
+                       reg = <0x0 0x22200000 0x0 0x1000>,
+                             <0x0 0x23006000 0x0 0x1000>;
+                       clocks = <&clk_mmc>;
+                       clock-names = "core";
+                       dma-coherent;
+                       interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+                       max-frequency = <200000000>;
+                       status = "disabled";
+               };
+
                gic: interrupt-controller@32800000 {
                        compatible = "arm,gic-v3";
                        reg = <0x0 0x32800000 0x0 0x10000>,