arm64: dts: ti: k3-j784s4-j742s2-main-common.dtsi: Refactor watchdog instances for...

Each A72 core has one watchdog instance associated with it. Since j742s2
has 4 A72 cores, the common file should not define 8 watchdog instances.

Refactor the last 4 extra watchdogs from the common file to j784s4
specific file, as j784s4 has 8 A72 cores and thus hardware description
requires 8 watchdog instances.

Fixes: 9cc161a4509c ("arm64: dts: ti: Refactor J784s4 SoC files to a common file")
Signed-off-by: Abhash Kumar Jha <a-kumar2@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Link: https://patch.msgid.link/20260112085113.3476193-3-a-kumar2@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
index 9cc0901d58fbf96bf6a8c7fd128694d53f319b69..c2636e624f18ba29d3241f52d553980720d57ef4 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
@@ -2378,42 +2378,6 @@
                assigned-clock-parents = <&k3_clks 351 4>;
        };
 
-       watchdog4: watchdog@2240000 {
-               compatible = "ti,j7-rti-wdt";
-               reg = <0x00 0x2240000 0x00 0x100>;
-               clocks = <&k3_clks 352 0>;
-               power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
-               assigned-clocks = <&k3_clks 352 0>;
-               assigned-clock-parents = <&k3_clks 352 4>;
-       };
-
-       watchdog5: watchdog@2250000 {
-               compatible = "ti,j7-rti-wdt";
-               reg = <0x00 0x2250000 0x00 0x100>;
-               clocks = <&k3_clks 353 0>;
-               power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
-               assigned-clocks = <&k3_clks 353 0>;
-               assigned-clock-parents = <&k3_clks 353 4>;
-       };
-
-       watchdog6: watchdog@2260000 {
-               compatible = "ti,j7-rti-wdt";
-               reg = <0x00 0x2260000 0x00 0x100>;
-               clocks = <&k3_clks 354 0>;
-               power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
-               assigned-clocks = <&k3_clks 354 0>;
-               assigned-clock-parents = <&k3_clks 354 4>;
-       };
-
-       watchdog7: watchdog@2270000 {
-               compatible = "ti,j7-rti-wdt";
-               reg = <0x00 0x2270000 0x00 0x100>;
-               clocks = <&k3_clks 355 0>;
-               power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
-               assigned-clocks = <&k3_clks 355 0>;
-               assigned-clock-parents = <&k3_clks 355 4>;
-       };
-
        /*
         * The following RTI instances are coupled with MCU R5Fs, c7x and
         * GPU so keeping them reserved as these will be used by their

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 5b7830a3c0975ba20b3cfc6038fd6990979c8ab5..78fcd0c40abcfa80e75b26b8666cdd46b2c06e67 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -6,6 +6,42 @@
  */
 
 &cbass_main {
+       watchdog4: watchdog@2240000 {
+               compatible = "ti,j7-rti-wdt";
+               reg = <0x00 0x2240000 0x00 0x100>;
+               clocks = <&k3_clks 352 0>;
+               power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
+               assigned-clocks = <&k3_clks 352 0>;
+               assigned-clock-parents = <&k3_clks 352 4>;
+       };
+
+       watchdog5: watchdog@2250000 {
+               compatible = "ti,j7-rti-wdt";
+               reg = <0x00 0x2250000 0x00 0x100>;
+               clocks = <&k3_clks 353 0>;
+               power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
+               assigned-clocks = <&k3_clks 353 0>;
+               assigned-clock-parents = <&k3_clks 353 4>;
+       };
+
+       watchdog6: watchdog@2260000 {
+               compatible = "ti,j7-rti-wdt";
+               reg = <0x00 0x2260000 0x00 0x100>;
+               clocks = <&k3_clks 354 0>;
+               power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
+               assigned-clocks = <&k3_clks 354 0>;
+               assigned-clock-parents = <&k3_clks 354 4>;
+       };
+
+       watchdog7: watchdog@2270000 {
+               compatible = "ti,j7-rti-wdt";
+               reg = <0x00 0x2270000 0x00 0x100>;
+               clocks = <&k3_clks 355 0>;
+               power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
+               assigned-clocks = <&k3_clks 355 0>;
+               assigned-clock-parents = <&k3_clks 355 4>;
+       };
+
        pcie2_rc: pcie@2920000 {
                compatible = "ti,j784s4-pcie-host";
                reg = <0x00 0x02920000 0x00 0x1000>,