reg = <0x0 0x48000000 0x1 0xf8000000>;
};
+ pcie_refclk: clock-pcie-ref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
reg_0p8v: regulator-0p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-0.8V";
status = "okay";
};
+&pcie {
+ pinctrl-0 = <&pcie_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pcie_port0 {
+ clocks = <&pcie_refclk>;
+ clock-names = "ref";
+};
+
&pinctrl {
eth0_pins: eth0 {
pins = "ET0_TXC_TXCLK";
<RZV2N_PORT_PINMUX(0, 7, 1)>; /* I2C8_SCL */
};
+ pcie_pins: pcie {
+ pins = "PCIE0_RSTOUTB";
+ slew-rate = <0>;
+ renesas,output-impedance = <2>;
+ };
+
scif_pins: scif {
pins = "SCIF_TXD", "SCIF_RXD";
renesas,output-impedance = <1>;