net: dsa: microchip: Use regs[] to access REG_PTP_CLK_CTRL

Accesses to the PTP_CLK_CTRL register are done through a hardcoded
address which doesn't match with the KSZ8463's register layout.

Add a new entry for the PTP_CLK_CTRL register in the regs[] tables.
Use the regs[] table to retrieve the PTP_CLK_CTRL register address
when accessing it.
Remove the macro defining the address to prevent further use.

Signed-off-by: Bastien Curutchet (Schneider Electric) <bastien.curutchet@bootlin.com>
Link: https://patch.msgid.link/20260105-ksz-rework-v1-3-a68df7f57375@bootlin.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>

diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index fa392f952f9441cfbeb51498fc9411340b58747a..d7f407370c1cc59402d444e27ebe44e7a600b441 100644 (file)
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -569,6 +569,7 @@ static const u16 ksz8463_regs[] = {
        [S_START_CTRL]                  = 0x01,
        [S_BROADCAST_CTRL]              = 0x06,
        [S_MULTICAST_CTRL]              = 0x04,
+       [PTP_CLK_CTRL]                  = 0x0600,
 };
 
 static const u32 ksz8463_masks[] = {
@@ -803,6 +804,7 @@ static const u16 ksz9477_regs[] = {
        [REG_SW_PME_CTRL]               = 0x0006,
        [REG_PORT_PME_STATUS]           = 0x0013,
        [REG_PORT_PME_CTRL]             = 0x0017,
+       [PTP_CLK_CTRL]                  = 0x0500,
 };
 
 static const u32 ksz9477_masks[] = {

diff --git a/drivers/net/dsa/microchip/ksz_common.h b/drivers/net/dsa/microchip/ksz_common.h
index 3add190e686260bb1807ba03b4b153abeead223e..8033cb9d84838705389e6ed52a5a54aaa8b49497 100644 (file)
--- a/drivers/net/dsa/microchip/ksz_common.h
+++ b/drivers/net/dsa/microchip/ksz_common.h
@@ -271,6 +271,7 @@ enum ksz_regs {
        REG_SW_PME_CTRL,
        REG_PORT_PME_STATUS,
        REG_PORT_PME_CTRL,
+       PTP_CLK_CTRL,
 };
 
 enum ksz_masks {

diff --git a/drivers/net/dsa/microchip/ksz_ptp.c b/drivers/net/dsa/microchip/ksz_ptp.c
index 0ac2865ba9c000fa58b974647c9c88287164cd1c..68553d9f1e0e3a3cd6319d73b7f9bf6ee2fce7ce 100644 (file)
--- a/drivers/net/dsa/microchip/ksz_ptp.c
+++ b/drivers/net/dsa/microchip/ksz_ptp.c
@@ -585,13 +585,14 @@ void ksz_port_deferred_xmit(struct kthread_work *work)
 
 static int _ksz_ptp_gettime(struct ksz_device *dev, struct timespec64 *ts)
 {
+       const u16 *regs = dev->info->regs;
        u32 nanoseconds;
        u32 seconds;
        u8 phase;
        int ret;
 
        /* Copy current PTP clock into shadow registers and read */
-       ret = ksz_rmw16(dev, REG_PTP_CLK_CTRL, PTP_READ_TIME, PTP_READ_TIME);
+       ret = ksz_rmw16(dev, regs[PTP_CLK_CTRL], PTP_READ_TIME, PTP_READ_TIME);
        if (ret)
                return ret;
 
@@ -676,6 +677,7 @@ static int ksz_ptp_settime(struct ptp_clock_info *ptp,
 {
        struct ksz_ptp_data *ptp_data = ptp_caps_to_data(ptp);
        struct ksz_device *dev = ptp_data_to_ksz_dev(ptp_data);
+       const u16 *regs = dev->info->regs;
        int ret;
 
        mutex_lock(&ptp_data->lock);
@@ -693,7 +695,7 @@ static int ksz_ptp_settime(struct ptp_clock_info *ptp,
        if (ret)
                goto unlock;
 
-       ret = ksz_rmw16(dev, REG_PTP_CLK_CTRL, PTP_LOAD_TIME, PTP_LOAD_TIME);
+       ret = ksz_rmw16(dev, regs[PTP_CLK_CTRL], PTP_LOAD_TIME, PTP_LOAD_TIME);
        if (ret)
                goto unlock;
 
@@ -723,6 +725,7 @@ static int ksz_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
 {
        struct ksz_ptp_data *ptp_data = ptp_caps_to_data(ptp);
        struct ksz_device *dev = ptp_data_to_ksz_dev(ptp_data);
+       const u16 *regs = dev->info->regs;
        u64 base, adj;
        bool negative;
        u32 data32;
@@ -743,12 +746,12 @@ static int ksz_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
                if (ret)
                        goto unlock;
 
-               ret = ksz_rmw16(dev, REG_PTP_CLK_CTRL, PTP_CLK_ADJ_ENABLE,
+               ret = ksz_rmw16(dev, regs[PTP_CLK_CTRL], PTP_CLK_ADJ_ENABLE,
                                PTP_CLK_ADJ_ENABLE);
                if (ret)
                        goto unlock;
        } else {
-               ret = ksz_rmw16(dev, REG_PTP_CLK_CTRL, PTP_CLK_ADJ_ENABLE, 0);
+               ret = ksz_rmw16(dev, regs[PTP_CLK_CTRL], PTP_CLK_ADJ_ENABLE, 0);
                if (ret)
                        goto unlock;
        }
@@ -763,6 +766,7 @@ static int ksz_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
        struct ksz_ptp_data *ptp_data = ptp_caps_to_data(ptp);
        struct ksz_device *dev = ptp_data_to_ksz_dev(ptp_data);
        struct timespec64 delta64 = ns_to_timespec64(delta);
+       const u16 *regs = dev->info->regs;
        s32 sec, nsec;
        u16 data16;
        int ret;
@@ -782,7 +786,7 @@ static int ksz_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
        if (ret)
                goto unlock;
 
-       ret = ksz_read16(dev, REG_PTP_CLK_CTRL, &data16);
+       ret = ksz_read16(dev, regs[PTP_CLK_CTRL], &data16);
        if (ret)
                goto unlock;
 
@@ -794,7 +798,7 @@ static int ksz_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
        else
                data16 |= PTP_STEP_DIR;
 
-       ret = ksz_write16(dev, REG_PTP_CLK_CTRL, data16);
+       ret = ksz_write16(dev, regs[PTP_CLK_CTRL], data16);
        if (ret)
                goto unlock;
 
@@ -882,9 +886,10 @@ out:
 static int ksz_ptp_start_clock(struct ksz_device *dev)
 {
        struct ksz_ptp_data *ptp_data = &dev->ptp_data;
+       const u16 *regs = dev->info->regs;
        int ret;
 
-       ret = ksz_rmw16(dev, REG_PTP_CLK_CTRL, PTP_CLK_ENABLE, PTP_CLK_ENABLE);
+       ret = ksz_rmw16(dev, regs[PTP_CLK_CTRL], PTP_CLK_ENABLE, PTP_CLK_ENABLE);
        if (ret)
                return ret;
 

diff --git a/drivers/net/dsa/microchip/ksz_ptp_reg.h b/drivers/net/dsa/microchip/ksz_ptp_reg.h
index d71e85510cda56b6ddfefd4ed65564dfb4be7c88..bf8526390c2a2face12406c575a1ea3e4d42e3e6 100644 (file)
--- a/drivers/net/dsa/microchip/ksz_ptp_reg.h
+++ b/drivers/net/dsa/microchip/ksz_ptp_reg.h
@@ -15,8 +15,7 @@
 #define LED_SRC_PTP_GPIO_2             BIT(2)
 
 /* 5 - PTP Clock */
-#define REG_PTP_CLK_CTRL               0x0500
-
+/* REG_PTP_CLK_CTRL */
 #define PTP_STEP_ADJ                   BIT(6)
 #define PTP_STEP_DIR                   BIT(5)
 #define PTP_READ_TIME                  BIT(4)