drm/sun4i: dsi: Restrict DSI tcon clock divider

[ Upstream commit 85fb352666732a9e5caf6027b9c253b3d7881d8f ]

The current code allows the TCON clock divider to have a range between 4
and 127 when feeding the DSI controller.

The only display supported so far had a display clock rate that ended up
using a divider of 4, but testing with other displays show that only 4
seems to be functional.

This also aligns with what Allwinner is doing in their BSP, so let's just
hardcode that we want a divider of 4 when using the DSI output.

Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/074e88ae472f5e0492e26939c74b44fb4125ffbd.1549896081.git-series.maxime.ripard@bootlin.com
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 7136fc91c6036cdb69d40a7d267ff5143c649d5c..e75f77ff8e0fc716e84263cea1ac56c2b0b00707 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -341,8 +341,8 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
        u32 block_space, start_delay;
        u32 tcon_div;
 
-       tcon->dclk_min_div = 4;
-       tcon->dclk_max_div = 127;
+       tcon->dclk_min_div = SUN6I_DSI_TCON_DIV;
+       tcon->dclk_max_div = SUN6I_DSI_TCON_DIV;
 
        sun4i_tcon0_mode_set_common(tcon, mode);
 

diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
index a07090579f84be286410e3a37c4668958bc5a3a0..5c3ad5be06901bc83179695f8ece7da02f9bf70c 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
@@ -13,6 +13,8 @@
 #include <drm/drm_encoder.h>
 #include <drm/drm_mipi_dsi.h>
 
+#define SUN6I_DSI_TCON_DIV     4
+
 struct sun6i_dsi {
        struct drm_connector    connector;
        struct drm_encoder      encoder;