clk: clocking-wizard: Fix output clock register offset for Versal platforms

[ Upstream commit 7c2e86f7b5af93d0e78c16e4359318fe7797671d ]

The output clock register offset used in clk_wzrd_register_output_clocks
was incorrectly referencing 0x3C instead of 0x38, which caused
misconfiguration of output dividers on Versal platforms.

Correcting the off-by-one error ensures proper configuration of output
clocks.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c
index 0295a13a811cf8e00fd49879eefc5bcf4fb89228..f209a02e82725ff2bfac373552ef92b15184a9b0 100644 (file)
--- a/drivers/clk/xilinx/clk-xlnx-clock-wizard.c
+++ b/drivers/clk/xilinx/clk-xlnx-clock-wizard.c
@@ -1108,7 +1108,7 @@ static int clk_wzrd_register_output_clocks(struct device *dev, int nr_outputs)
                                                (dev,
                                                 clkout_name, clk_name, 0,
                                                 clk_wzrd->base,
-                                                (WZRD_CLK_CFG_REG(is_versal, 3) + i * 8),
+                                                (WZRD_CLK_CFG_REG(is_versal, 2) + i * 8),
                                                 WZRD_CLKOUT_DIVIDE_SHIFT,
                                                 WZRD_CLKOUT_DIVIDE_WIDTH,
                                                 CLK_DIVIDER_ONE_BASED |