]> git.ipfire.org Git - thirdparty/gcc.git/commitdiff
AArch64: precommit test for masked load vectorisation.
authorKarl Meakin <karl.meakin@arm.com>
Tue, 15 Jul 2025 14:49:57 +0000 (14:49 +0000)
committerAlfie Richards <alfie.richards@arm.com>
Tue, 22 Jul 2025 15:01:12 +0000 (15:01 +0000)
Commit the test file `mask_load_2.c` before the vectorisation analysis
is changed, so that the changes in codegen are more obvious in the next
commit.

gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sve/mask_load_2.c: New test.

gcc/testsuite/gcc.target/aarch64/sve/mask_load_2.c [new file with mode: 0644]

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/mask_load_2.c b/gcc/testsuite/gcc.target/aarch64/sve/mask_load_2.c
new file mode 100644 (file)
index 0000000..38fcf4f
--- /dev/null
@@ -0,0 +1,23 @@
+// { dg-do compile }
+// { dg-options "-march=armv8-a+sve -msve-vector-bits=128 -O3" }
+
+typedef struct Array {
+    int elems[3];
+} Array;
+
+int loop(Array **pp, int len, int idx) {
+    int nRet = 0;
+
+    #pragma GCC unroll 0
+    for (int i = 0; i < len; i++) {
+        Array *p = pp[i];
+        if (p) {
+            nRet += p->elems[idx];
+        }
+    }
+
+    return nRet;
+}
+
+// { dg-final { scan-assembler-times {ld1w\tz[0-9]+\.d, p[0-7]/z} 0 } }
+// { dg-final { scan-assembler-times {add\tz[0-9]+\.s, p[0-7]/m}  0 } }