mips: add definitions for more MIPS processors

Add more constants to be used to differentiate MIPS processors in hwcaps.

git-svn-id: svn://svn.valgrind.org/vex/trunk@3204

diff --git a/VEX/priv/host_mips_isel.c b/VEX/priv/host_mips_isel.c
index 66b3014d04b9f6dfdf8154da7f0411e5d5a6131d..0cde325560a501a8cfdf3ab01856642b1487f873 100644 (file)
--- a/VEX/priv/host_mips_isel.c
+++ b/VEX/priv/host_mips_isel.c
@@ -4172,9 +4172,11 @@ HInstrArray *iselSB_MIPS ( const IRSB* bb,
    /* sanity ... */
    vassert(arch_host == VexArchMIPS32 || arch_host == VexArchMIPS64);
    vassert(VEX_PRID_COMP_MIPS == VEX_MIPS_COMP_ID(hwcaps_host)
+           || VEX_PRID_COMP_CAVIUM == VEX_MIPS_COMP_ID(hwcaps_host)
            || VEX_PRID_COMP_BROADCOM == VEX_MIPS_COMP_ID(hwcaps_host)
            || VEX_PRID_COMP_NETLOGIC == VEX_MIPS_COMP_ID(hwcaps_host)
-           || VEX_PRID_COMP_CAVIUM == VEX_MIPS_COMP_ID(hwcaps_host));
+           || VEX_PRID_COMP_INGENIC_E1 == VEX_MIPS_COMP_ID(hwcaps_host)
+           || VEX_PRID_COMP_LEGACY == VEX_MIPS_COMP_ID(hwcaps_host));
 
    /* Check that the host's endianness is as expected. */
    vassert(archinfo_host->endness == VexEndnessLE

diff --git a/VEX/priv/main_main.c b/VEX/priv/main_main.c
index 2e51ded787c2f7a38d187811fdec2396298217f1..119d70120fc91c31b40d9e0b706c73a33a2066c0 100644 (file)
--- a/VEX/priv/main_main.c
+++ b/VEX/priv/main_main.c
@@ -1706,11 +1706,38 @@ static const HChar* show_hwcaps_mips32 ( UInt hwcaps )
       return "Cavium-baseline";
    }
 
+   /* Ingenic baseline. */
+   if (VEX_MIPS_COMP_ID(hwcaps) == VEX_PRID_COMP_INGENIC_E1) {
+      return "Ingenic-baseline";
+   }
+
+   /* Loongson baseline. */
+   if ((VEX_MIPS_COMP_ID(hwcaps) == VEX_PRID_COMP_LEGACY) &&
+       (VEX_MIPS_PROC_ID(hwcaps) == VEX_PRID_IMP_LOONGSON_64)) {
+      return "Loongson-baseline";
+   }
+
    return "Unsupported baseline";
 }
 
 static const HChar* show_hwcaps_mips64 ( UInt hwcaps )
 {
+   /* Netlogic baseline. */
+   if (VEX_MIPS_COMP_ID(hwcaps) == VEX_PRID_COMP_NETLOGIC) {
+      return "Netlogic-baseline";
+   }
+
+   /* Cavium baseline. */
+   if (VEX_MIPS_COMP_ID(hwcaps) == VEX_PRID_COMP_CAVIUM) {
+      return "Cavium-baseline";
+   }
+
+   /* Loongson baseline. */
+   if ((VEX_MIPS_COMP_ID(hwcaps) == VEX_PRID_COMP_LEGACY) &&
+       (VEX_MIPS_PROC_ID(hwcaps) == VEX_PRID_IMP_LOONGSON_64)) {
+      return "Loongson-baseline";
+   }
+
    return "mips64-baseline";
 }
 
@@ -1908,19 +1935,28 @@ static void check_hwcaps ( VexArch arch, UInt hwcaps )
             invalid_hwcaps(arch, hwcaps,
                            "Host does not have long displacement facility.\n");
          return;
-        
+
       case VexArchMIPS32:
          switch (VEX_MIPS_COMP_ID(hwcaps)) {
             case VEX_PRID_COMP_MIPS:
+            case VEX_PRID_COMP_CAVIUM:
+            case VEX_PRID_COMP_INGENIC_E1:
             case VEX_PRID_COMP_BROADCOM:
             case VEX_PRID_COMP_NETLOGIC:
                return;
             default:
                invalid_hwcaps(arch, hwcaps, "Unsupported baseline\n");
          }
-      
+
       case VexArchMIPS64:
-         return;
+         switch (VEX_MIPS_COMP_ID(hwcaps)) {
+            case VEX_PRID_COMP_MIPS:
+            case VEX_PRID_COMP_CAVIUM:
+            case VEX_PRID_COMP_NETLOGIC:
+               return;
+            default:
+               invalid_hwcaps(arch, hwcaps, "Unsupported baseline\n");
+         }
 
       case VexArchTILEGX:
          return;

diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h
index b055c54cff57f91af905f3e390c23b2171893304..0388acc72e76332281aa9da753f91890443d33be 100644 (file)
--- a/VEX/pub/libvex.h
+++ b/VEX/pub/libvex.h
@@ -204,16 +204,23 @@ typedef
 
 */
 
-#define VEX_PRID_COMP_MIPS      0x00010000
-#define VEX_PRID_COMP_BROADCOM  0x00020000
-#define VEX_PRID_COMP_NETLOGIC  0x000C0000
-#define VEX_PRID_COMP_CAVIUM    0x000D0000
+#define VEX_PRID_COMP_LEGACY      0x00000000
+#define VEX_PRID_COMP_MIPS        0x00010000
+#define VEX_PRID_COMP_BROADCOM    0x00020000
+#define VEX_PRID_COMP_NETLOGIC    0x000C0000
+#define VEX_PRID_COMP_CAVIUM      0x000D0000
+#define VEX_PRID_COMP_INGENIC_E1  0x00E10000        /* JZ4780 */
+
+/*
+ * These are valid when 23:16 == PRID_COMP_LEGACY
+ */
+#define VEX_PRID_IMP_LOONGSON_64        0x6300  /* Loongson-2/3 */
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_MIPS
  */
-#define VEX_PRID_IMP_34K        0x9500
-#define VEX_PRID_IMP_74K        0x9700
+#define VEX_PRID_IMP_34K                0x9500
+#define VEX_PRID_IMP_74K                0x9700
 
 /* CPU has FPU and 32 dbl. prec. FP registers */
 #define VEX_PRID_CPU_32FPR      0x00000040