This is the minimal change beginning with TARGET_ARCH in
configs/targets/or1k-* from openrisc to or1k, then adjust
TARGET_OR1K, QEMU_ARCH_OR1K, directory names,
and meson.build to match.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <
20260205030244.266447-2-richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
M: Stafford Horne <shorne@gmail.com>
S: Odd Fixes
F: docs/system/openrisc/cpu-features.rst
-F: target/openrisc/
+F: target/or1k/
F: hw/openrisc/
F: include/hw/openrisc/
F: tests/functional/or1k/meson.build
-TARGET_ARCH=openrisc
+TARGET_ARCH=or1k
TARGET_BIG_ENDIAN=y
TARGET_SYSTBL_ABI=common,32,or1k,time32,stat64,rlimit,renameat
TARGET_SYSTBL=syscall.tbl
-TARGET_ARCH=openrisc
+TARGET_ARCH=or1k
TARGET_BIG_ENDIAN=y
# needed by boot.c and all boards
TARGET_NEED_FDT=y
config OR1K_SIM
bool
default y
- depends on OPENRISC
+ depends on OR1K
select DEVICE_TREE
select SERIAL_MM
select OPENCORES_ETH
config OR1K_VIRT
bool
default y
- depends on OPENRISC
+ depends on OR1K
imply PCI_DEVICES
imply VIRTIO_VGA
imply TEST_DEVICES
openrisc_ss.add(when: 'CONFIG_OR1K_SIM', if_true: files('openrisc_sim.c'))
openrisc_ss.add(when: 'CONFIG_OR1K_VIRT', if_true: files('virt.c'))
-hw_arch += {'openrisc': openrisc_ss}
+hw_arch += {'or1k': openrisc_ss}
#pragma GCC poison TARGET_ABI_MIPSO32
#pragma GCC poison TARGET_MIPS64
#pragma GCC poison TARGET_ABI_MIPSN64
-#pragma GCC poison TARGET_OPENRISC
+#pragma GCC poison TARGET_OR1K
#pragma GCC poison TARGET_PPC
#pragma GCC poison TARGET_PPC64
#pragma GCC poison TARGET_ABI32
QEMU_ARCH_SH4 = (1 << 10),
QEMU_ARCH_SPARC = (1 << 11),
QEMU_ARCH_XTENSA = (1 << 12),
- QEMU_ARCH_OPENRISC = (1 << 13),
+ QEMU_ARCH_OR1K = (1 << 13),
QEMU_ARCH_TRICORE = (1 << 16),
QEMU_ARCH_HPPA = (1 << 18),
QEMU_ARCH_RISCV = (1 << 19),
#if (defined(TARGET_I386) && !defined(TARGET_X86_64)) \
|| defined(TARGET_SH4) \
- || defined(TARGET_OPENRISC) \
+ || defined(TARGET_OR1K) \
|| defined(TARGET_MICROBLAZE)
#define ABI_LLONG_ALIGNMENT 4
#endif
subdir('microblaze')
subdir('mips64')
subdir('mips')
-subdir('openrisc')
+subdir('or1k')
subdir('ppc')
subdir('riscv')
subdir('s390x')
+++ /dev/null
-syscall_nr_generators += {
- 'openrisc': generator(sh,
- arguments: [ meson.current_source_dir() / 'syscallhdr.sh', '@INPUT@', '@OUTPUT@', '@EXTRA_ARGS@' ],
- output: '@BASENAME@_nr.h')
-}
--- /dev/null
+syscall_nr_generators += {
+ 'or1k': generator(sh,
+ arguments: [ meson.current_source_dir() / 'syscallhdr.sh', '@INPUT@', '@OUTPUT@', '@EXTRA_ARGS@' ],
+ output: '@BASENAME@_nr.h')
+}
#if defined(TARGET_I386) || defined(TARGET_ARM) || defined(TARGET_SH4) \
|| defined(TARGET_M68K) \
- || defined(TARGET_S390X) || defined(TARGET_OPENRISC) \
+ || defined(TARGET_S390X) || defined(TARGET_OR1K) \
|| defined(TARGET_RISCV) \
|| defined(TARGET_XTENSA) || defined(TARGET_LOONGARCH64)
abi_ulong __unused5;
};
-#elif defined(TARGET_OPENRISC) \
+#elif defined(TARGET_OR1K) \
|| defined(TARGET_RISCV) || defined(TARGET_HEXAGON) || defined(TARGET_LOONGARCH)
/* These are the asm-generic versions of the stat and stat64 structures */
QEMU_ARCH_I386 | \
QEMU_ARCH_LOONGARCH | \
QEMU_ARCH_MIPS | \
- QEMU_ARCH_OPENRISC | \
+ QEMU_ARCH_OR1K | \
QEMU_ARCH_PPC | \
QEMU_ARCH_RISCV | \
QEMU_ARCH_SH4 | \
source m68k/Kconfig
source microblaze/Kconfig
source mips/Kconfig
-source openrisc/Kconfig
+source or1k/Kconfig
source ppc/Kconfig
source riscv/Kconfig
source rx/Kconfig
subdir('m68k')
subdir('microblaze')
subdir('mips')
-subdir('openrisc')
+subdir('or1k')
subdir('ppc')
subdir('riscv')
subdir('rx')
-config OPENRISC
+config OR1K
bool
select DEVICE_TREE # needed by boot.c
'mmu.c',
))
-target_arch += {'openrisc': openrisc_ss}
-target_common_system_arch += {'openrisc': openrisc_system_ss}
+target_arch += {'or1k': openrisc_ss}
+target_common_system_arch += {'or1k': openrisc_system_ss}