ranges = <0x5c000000 0x0 0x5c000000 0x1000000>;
ddr_pmu0: ddr-pmu@5c020000 {
- compatible = "fsl,imx8-ddr-pmu";
+ compatible = "fsl,imx8qxp-ddr-pmu", "fsl,imx8-ddr-pmu";
reg = <0x5c020000 0x10000>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+&ddr_pmu0 {
+ compatible = "fsl,imx8qm-ddr-pmu", "fsl,imx8-ddr-pmu";
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&ddr_subsys {
+ ddr_pmu1: ddr-pmu@5c120000 {
+ compatible = "fsl,imx8qm-ddr-pmu", "fsl,imx8-ddr-pmu";
+ reg = <0x5c120000 0x10000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
#include "imx8-ss-img.dtsi"
#include "imx8-ss-dma.dtsi"
#include "imx8-ss-conn.dtsi"
+ #include "imx8-ss-ddr.dtsi"
#include "imx8-ss-lsio.dtsi"
#include "imx8-ss-hsio.dtsi"
};
#include "imx8qm-ss-lvds.dtsi"
#include "imx8qm-ss-mipi.dtsi"
#include "imx8qm-ss-hsio.dtsi"
+#include "imx8qm-ss-ddr.dtsi"
/delete-node/ &dsp;