]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
drm/imagination: Skip 2nd thread DM association for non META Firmware
authorBrajesh Gupta <brajesh.gupta@imgtec.com>
Fri, 13 Mar 2026 06:38:25 +0000 (06:38 +0000)
committerMatt Coster <matt.coster@imgtec.com>
Mon, 23 Mar 2026 15:02:05 +0000 (15:02 +0000)
Only a META firmware can have two threads.

Signed-off-by: Brajesh Gupta <brajesh.gupta@imgtec.com>
Reviewed-by: Matt Coster <matt.coster@imgtec.com>
Link: https://patch.msgid.link/20260313-b4-staging-layout_mars_base-v2-2-9e3c251d278e@imgtec.com
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
drivers/gpu/drm/imagination/pvr_fw_startstop.c

index 6ae0489f7e2ed73d390bd026954e7fbd617cf152..e24ed6fc4362f3c86c439a8b6a39ec800d5e1167 100644 (file)
@@ -243,12 +243,15 @@ pvr_fw_stop(struct pvr_device *pvr_dev)
        pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC,
                       ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_MASKFULL &
                       ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK);
-       pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC,
-                      ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL &
-                      ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK);
-       pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC,
-                      ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL &
-                      ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK);
+
+       if (meta_fw) {
+               pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC,
+                              ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL &
+                              ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK);
+               pvr_cr_write32(pvr_dev, ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC,
+                              ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL &
+                              ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK);
+       }
 
        /* Extra Idle checks. */
        err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_BIF_STATUS_MMU, 0,